View H838602R_4699608.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

REJ09B0152-0300
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
16
H8/38602RGroup
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series H8/38602R H8/38600R HD64F38602R HD64338602R HD64338600R
Rev.3.00 Revision Date: May 15, 2007
Rev. 3.00 May 15, 2007 Page ii of xxxii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 3.00 May 15, 2007 Page iii of xxxii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 3.00 May 15, 2007 Page iv of xxxii
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index
Rev. 3.00 May 15, 2007 Page v of xxxii
Preface
The H8/38602R Group consists of single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/38602R Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8/38602R Group to the target users. Refer to the H8/300H Series Software Manual for a detailed description of the instruction set.
Notes on reading this manual: In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions, and electrical characteristics. In order to understand the details of the CPU's functions Read the H8/300H Series Software Manual. In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 20, List of Registers. Example: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right.
Bit order:
Rev. 3.00 May 15, 2007 Page vi of xxxii
Notes: When using an on-chip emulator (E7) for H8/38602R program development and debugging, the following restrictions must be noted. The NMI pin is reserved for the E7, and cannot be used. Area H'4000 to H'4FFF should not be accessed. Area H'F780 to H'FB7F should not be accessed. When the E7 is used, NMI is an input/output pin (open-drain in output mode). When on-board programming/erasing is performed in boot mode, the SCI3 (P31/RXD3 and P32/TXD3) is used. 6. When the on-chip emulator is used, even though the on-chip oscillator is selected, connect a resonator to OSC1 and OSC2 or input an external clock to OSC1. 7. When using the E7, set the FROMCKSTP bit in clock halt register 1 to 1. 1. 2. 3. 4. 5. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/
H8/38602R Group manuals:
Document Title H8/38602R Group Hardware Manual H8/300H Series Software Manual Document No. This manual REJ09B0213
User's manuals for development tools:
Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial Document No. REJ10B0058 ADE-702-282 REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual REJ10B0026
Rev. 3.00 May 15, 2007 Page vii of xxxii
Application notes:
Document Title F-ZTAT Microcomputer On-Board Programming Document No. REJ05B0523
All trademarks and registered trademarks are the property of their respective owners.
Rev. 3.00 May 15, 2007 Page viii of xxxii
Contents
Section 1 Overview................................................................................................1
1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 2 Pin Assignment ...................................................................................................................... 3 Pin Functions ......................................................................................................................... 4
Section 2 CPU........................................................................................................7
2.1 2.2 Address Space and Memory Map .......................................................................................... 8 Register Configuration........................................................................................................... 9 2.2.1 General Registers.................................................................................................... 10 2.2.2 Program Counter (PC) ............................................................................................ 11 2.2.3 Condition-Code Register (CCR)............................................................................. 11 Data Formats........................................................................................................................ 13 2.3.1 General Register Data Formats ............................................................................... 13 2.3.2 Memory Data Formats ............................................................................................ 15 Instruction Set ...................................................................................................................... 16 2.4.1 Table of Instructions Classified by Function .......................................................... 16 2.4.2 Basic Instruction Formats ....................................................................................... 26 Addressing Modes and Effective Address Calculation........................................................ 27 2.5.1 Addressing Modes .................................................................................................. 27 2.5.2 Effective Address Calculation ................................................................................ 30 Basic Bus Cycle ................................................................................................................... 32 2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 32 2.6.2 On-Chip Peripheral Modules .................................................................................. 33 CPU States ........................................................................................................................... 34 Usage Notes ......................................................................................................................... 35 2.8.1 Notes on Data Access to Empty Areas ................................................................... 35 2.8.2 EEPMOV Instruction.............................................................................................. 35 2.8.3 Bit-Manipulation Instruction .................................................................................. 36
2.3
2.4
2.5
2.6
2.7 2.8
Section 3 Exception Handling .............................................................................41
3.1 3.2 Exception Sources and Vector Address ............................................................................... 42 Reset .................................................................................................................................... 44 3.2.1 Reset Exception Handling....................................................................................... 44 3.2.2 Interrupt Immediately after Reset ........................................................................... 45 Input/Output Pins ................................................................................................................. 46
3.3
Rev. 3.00 May 15, 2007 Page ix of xxxii
3.4
3.5
3.6 3.7 3.8
Register Descriptions........................................................................................................... 46 3.4.1 Interrupt Edge Select Register (IEGR) ................................................................... 47 3.4.2 Interrupt Enable Register 1 (IENR1) ...................................................................... 48 3.4.3 Interrupt Enable Register 2 (IENR2) ...................................................................... 49 3.4.4 Interrupt Flag Register 1 (IRR1)............................................................................. 50 3.4.5 Interrupt Flag Register 2 (IRR2)............................................................................. 51 Interrupt Sources.................................................................................................................. 52 3.5.1 External Interrupts .................................................................................................. 52 3.5.2 Internal Interrupts ................................................................................................... 53 Operation ............................................................................................................................. 53 3.6.1 Interrupt Exception Handling Sequence ................................................................. 56 Stack Status after Exception Handling................................................................................. 57 3.7.1 Interrupt Response Time......................................................................................... 57 Usage Notes ......................................................................................................................... 58 3.8.1 Notes on Stack Area Use ........................................................................................ 58 3.8.2 Notes on Switching Functions of External Interrupt Pins....................................... 59 3.8.3 Method for Clearing Interrupt Request Flags ......................................................... 60 3.8.4 Conflict between Interrupt Generation and Disabling ............................................ 60 3.8.5 Instructions that Disable Interrupts......................................................................... 61 3.8.6 Interrupts during Execution of EEPMOV Instruction ............................................ 61 3.8.7 IENR Clearing ........................................................................................................ 61
Section 4 Clock Pulse Generators ....................................................................... 63
4.1 4.2 Register Description ............................................................................................................ 64 4.1.1 Oscillator Control Register (OSCCR) .................................................................... 64 System Clock Oscillator ...................................................................................................... 66 4.2.1 Connecting Crystal Resonator ................................................................................ 66 4.2.2 Connecting Ceramic Resonator .............................................................................. 66 4.2.3 External Clock Input Method ................................................................................. 67 4.2.4 On-Chip Oscillator Selection Method .................................................................... 67 Subclock Oscillator.............................................................................................................. 68 4.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator ............................................ 68 4.3.2 Pin Connection when not Using Subclock.............................................................. 69 4.3.3 External Clock Input Method ................................................................................. 70 4.3.4 On-Chip Oscillator Selection Method .................................................................... 70 Prescalers ............................................................................................................................. 71 4.4.1 Prescaler S .............................................................................................................. 71 4.4.2 Prescaler W............................................................................................................. 71 Usage Notes ......................................................................................................................... 72 4.5.1 Note on Resonators and Resonator Circuits ........................................................... 72
4.3
4.4
4.5
Rev. 3.00 May 15, 2007 Page x of xxxii
4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7
Notes on Board Design ........................................................................................... 74 Definition of Oscillation Stabilization Wait Time .................................................. 74 Note on Subclock Stop State................................................................................... 76 Note on the Oscillation Stabilization of Resonators ............................................... 76 Note on Using Power-On Reset .............................................................................. 76 Note on Using On-Chip Emulator .......................................................................... 76
Section 5 Power-Down Modes ............................................................................77
5.1 Register Descriptions ........................................................................................................... 78 5.1.1 System Control Register 1 (SYSCR1) .................................................................... 78 5.1.2 System Control Register 2 (SYSCR2) .................................................................... 80 5.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) ..................................... 81 Mode Transitions and States of LSI..................................................................................... 83 5.2.1 Sleep Mode ............................................................................................................. 87 5.2.2 Standby Mode ......................................................................................................... 88 5.2.3 Watch Mode............................................................................................................ 88 5.2.4 Subsleep Mode........................................................................................................ 89 5.2.5 Subactive Mode ...................................................................................................... 89 5.2.6 Active (Medium-Speed) Mode ............................................................................... 90 Direct Transition .................................................................................................................. 91 5.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode ................................................................. 91 5.3.2 Direct Transition from Active (High-Speed) Mode to Subactive Mode................. 92 5.3.3 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode ...................................................................... 92 5.3.4 Direct Transition from Active (Medium-Speed) Mode to Subactive Mode ........... 93 5.3.5 Direct Transition from Subactive Mode to Active (High-Speed) Mode................. 93 5.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode ........... 94 5.3.7 Notes on External Input Signal Changes before/after Direct Transition................. 95 Module Standby Function.................................................................................................... 96 On-Chip Oscillator and Operation Mode ............................................................................. 96 Usage Notes ......................................................................................................................... 97 5.6.1 Standby Mode Transition and Pin States ................................................................ 97 5.6.2 Notes on External Input Signal Changes before/after Standby Mode..................... 97
5.2
5.3
5.4 5.5 5.6
Section 6 ROM ....................................................................................................99
6.1 6.2 Block Configuration........................................................................................................... 100 Register Descriptions ......................................................................................................... 101 6.2.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 101 6.2.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 102
Rev. 3.00 May 15, 2007 Page xi of xxxii
6.3
6.4
6.5
6.6 6.7
6.2.3 Erase Block Register 1 (EBR1) ............................................................................ 103 6.2.4 Flash Memory Power Control Register (FLPWCR)............................................. 103 6.2.5 Flash Memory Enable Register (FENR)............................................................... 104 On-Board Programming Modes......................................................................................... 104 6.3.1 Boot Mode ............................................................................................................ 105 6.3.2 Programming/Erasure in User Program Mode...................................................... 108 Flash Memory Programming/Erasure................................................................................ 109 6.4.1 Programming/Programming-Verifying................................................................. 109 6.4.2 Erasing/Erasing-Verifying .................................................................................... 112 6.4.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 112 Programming/Erasing Protection....................................................................................... 114 6.5.1 Hardware Protection ............................................................................................. 114 6.5.2 Software Protection .............................................................................................. 114 6.5.3 Error Protection .................................................................................................... 114 Power-Down States for Flash Memory.............................................................................. 115 Notes on Setting Module Standby Mode ........................................................................... 116
Section 7 RAM .................................................................................................. 117 Section 8 I/O Ports............................................................................................. 119
8.1 Port 1.................................................................................................................................. 119 8.1.1 Port Data Register 1 (PDR1) ................................................................................ 120 8.1.2 Port Control Register 1 (PCR1) ............................................................................ 120 8.1.3 Port Pull-Up Control Register 1 (PUCR1)............................................................ 121 8.1.4 Port Mode Register 1 (PMR1) .............................................................................. 121 8.1.5 Pin Functions ........................................................................................................ 122 8.1.6 Input Pull-Up MOS............................................................................................... 124 Port 3.................................................................................................................................. 124 8.2.1 Port Data Register 3 (PDR3) ................................................................................ 125 8.2.2 Port Control Register 3 (PCR3) ............................................................................ 125 8.2.3 Port Pull-Up Control Register 3 (PUCR3)............................................................ 126 8.2.4 Port Mode Register 3 (PMR3) .............................................................................. 126 8.2.5 Pin Functions ........................................................................................................ 127 8.2.6 Input Pull-Up MOS............................................................................................... 128 Port 8.................................................................................................................................. 128 8.3.1 Port Data Register 8 (PDR8) ................................................................................ 129 8.3.2 Port Control Register 8 (PCR8) ............................................................................ 129 8.3.3 Port Pull-Up Control Register 8 (PUCR8)............................................................ 130 8.3.4 Pin Functions ........................................................................................................ 130 8.3.5 Input Pull-Up MOS............................................................................................... 132
8.2
8.3
Rev. 3.00 May 15, 2007 Page xii of xxxii
8.4
8.5
8.6
8.7
Port 9.................................................................................................................................. 132 8.4.1 Port Data Register 9 (PDR9)................................................................................. 133 8.4.2 Port Control Register 9 (PCR9) ............................................................................ 133 8.4.3 Port Open-Drain Control Register 9 (PODR9) ..................................................... 134 8.4.4 Port Pull-Up Control Register 9 (PUCR9)............................................................ 134 8.4.5 Pin Functions ........................................................................................................ 135 8.4.6 Input Pull-Up MOS............................................................................................... 137 Port B ................................................................................................................................. 138 8.5.1 Port Data Register B (PDRB) ............................................................................... 138 8.5.2 Port Mode Register B (PMRB)............................................................................. 139 8.5.3 Pin Functions ........................................................................................................ 140 Input/Output Data Inversion .............................................................................................. 142 8.6.1 Serial Port Control Register (SPCR)..................................................................... 142 8.6.2 Port Function Control Register (PFCR)................................................................ 143 Usage Notes ....................................................................................................................... 144 8.7.1 How to Handle Unused Pin................................................................................... 144 8.7.2 Input Characteristics Difference due to Pin Function ........................................... 144
Section 9 Timer B1 ............................................................................................145
9.1 9.2 Features.............................................................................................................................. 145 Register Descriptions ......................................................................................................... 146 9.2.1 Timer Mode Register B1 (TMB1) ........................................................................ 146 9.2.2 Timer Counter B1 (TCB1).................................................................................... 147 9.2.3 Timer Load Register B1 (TLB1) .......................................................................... 147 Usage Method .................................................................................................................... 148 Operation ........................................................................................................................... 150 9.4.1 Interval Timer Operation ...................................................................................... 150 9.4.2 Auto-Reload Timer Operation .............................................................................. 150 Timer B1 Operating Modes ............................................................................................... 151
9.3 9.4
9.5
Section 10 Timer W ...........................................................................................153
10.1 Features.............................................................................................................................. 153 10.2 Input/Output Pins ............................................................................................................... 156 10.3 Register Descriptions ......................................................................................................... 156 10.3.1 Timer Mode Register W (TMRW) ....................................................................... 157 10.3.2 Timer Control Register W (TCRW) ..................................................................... 158 10.3.3 Timer Interrupt Enable Register W (TIERW) ...................................................... 159 10.3.4 Timer Status Register W (TSRW) ........................................................................ 160 10.3.5 Timer I/O Control Register 0 (TIOR0) ................................................................. 161 10.3.6 Timer I/O Control Register 1 (TIOR1) ................................................................. 163
Rev. 3.00 May 15, 2007 Page xiii of xxxii
10.4
10.5
10.6 10.7
10.3.7 Timer Counter (TCNT)......................................................................................... 164 10.3.8 General Registers A to D (GRA to GRD)............................................................. 165 Operation ........................................................................................................................... 166 10.4.1 Normal Operation ................................................................................................. 166 10.4.2 PWM Operation.................................................................................................... 170 Operation Timing............................................................................................................... 175 10.5.1 TCNT Count Timing ............................................................................................ 175 10.5.2 Output Compare Output Timing........................................................................... 176 10.5.3 Input Capture Timing ........................................................................................... 177 10.5.4 Timing of Counter Clearing by Compare Match .................................................. 177 10.5.5 Buffer Operation Timing ...................................................................................... 178 10.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ................................. 179 10.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................. 180 10.5.8 Timing of Status Flag Clearing............................................................................. 180 Timer W Operating Modes ................................................................................................ 181 Usage Notes ....................................................................................................................... 181
Section 11 Realtime Clock (RTC)..................................................................... 185
11.1 Features.............................................................................................................................. 185 11.2 Input/Output Pin ................................................................................................................ 186 11.3 Register Descriptions......................................................................................................... 187 11.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) ............. 187 11.3.2 Minute Data Register (RMINDR) ........................................................................ 188 11.3.3 Hour Data Register (RHRDR) .............................................................................. 189 11.3.4 Day-of-Week Data Register (RWKDR) ............................................................... 190 11.3.5 RTC Control Register 1 (RTCCR1) ..................................................................... 191 11.3.6 RTC Control Register 2 (RTCCR2) ..................................................................... 192 11.3.7 Clock Source Select Register (RTCCSR)............................................................. 193 11.3.8 RTC Interrupt Flag Register (RTCFLG) .............................................................. 194 11.4 Operation ........................................................................................................................... 196 11.4.1 Initial Settings of Registers after Power-On ......................................................... 196 11.4.2 Initial Setting Procedure ....................................................................................... 196 11.4.3 Data Reading Procedure ....................................................................................... 197 11.5 Interrupt Sources................................................................................................................ 198 11.6 Usage Notes ....................................................................................................................... 199 11.6.1 Note on Clock Count ............................................................................................ 199 11.6.2 Note when Using RTC Interrupts ......................................................................... 199
Section 12 Watchdog Timer.............................................................................. 201
12.1 Features.............................................................................................................................. 201
Rev. 3.00 May 15, 2007 Page xiv of xxxii
12.2 Register Descriptions ......................................................................................................... 202 12.2.1 Timer Control/Status Register WD1 (TCSRWD1)............................................... 203 12.2.2 Timer Control/Status Register WD2 (TCSRWD2)............................................... 205 12.2.3 Timer Counter WD (TCWD)................................................................................ 206 12.2.4 Timer Mode Register WD (TMWD) .................................................................... 207 12.3 Operation ........................................................................................................................... 208 12.3.1 Watchdog Timer Mode ......................................................................................... 208 12.3.2 Interval Timer Mode............................................................................................. 209 12.3.3 Timing of Overflow Flag (OVF) Setting .............................................................. 209 12.4 Interrupt ............................................................................................................................. 210 12.5 Usage Notes ....................................................................................................................... 210 12.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode................. 210 12.5.2 Module Standby Mode Control............................................................................. 210 12.5.3 Clearing the WT/IT or IEOVF Bit in TCSRWD2 to 0 ......................................... 210
Section 13 Asynchronous Event Counter (AEC) ..............................................213
13.1 Features.............................................................................................................................. 213 13.2 Input/Output Pins ............................................................................................................... 215 13.3 Register Descriptions ......................................................................................................... 215 13.3.1 Event Counter PWM Compare Register (ECPWCR) ........................................... 216 13.3.2 Event Counter PWM Data Register (ECPWDR).................................................. 217 13.3.3 Input Pin Edge Select Register (AEGSR)............................................................. 218 13.3.4 Event Counter Control Register (ECCR).............................................................. 219 13.3.5 Event Counter Control/Status Register (ECCSR)................................................. 220 13.3.6 Event Counter H (ECH)........................................................................................ 222 13.3.7 Event Counter L (ECL)......................................................................................... 222 13.4 Operation ........................................................................................................................... 223 13.4.1 16-Bit Counter Operation ..................................................................................... 223 13.4.2 8-Bit Counter Operation ....................................................................................... 224 13.4.3 IRQAEC Operation............................................................................................... 225 13.4.4 Event Counter PWM Operation............................................................................ 225 13.4.5 Operation of Clock Input Enable/Disable Function.............................................. 227 13.5 Operating States of Asynchronous Event Counter............................................................. 228 13.6 Usage Notes ....................................................................................................................... 229
Section 14 Serial Communication Interface 3 (SCI3, IrDA).............................231
14.1 Features.............................................................................................................................. 231 14.2 Input/Output Pins ............................................................................................................... 233 14.3 Register Descriptions ......................................................................................................... 233 14.3.1 Receive Shift Register (RSR) ............................................................................... 234
Rev. 3.00 May 15, 2007 Page xv of xxxii
14.4
14.5
14.6
14.7 14.8
14.3.2 Receive Data Register (RDR)............................................................................... 234 14.3.3 Transmit Shift Register (TSR) .............................................................................. 234 14.3.4 Transmit Data Register (TDR).............................................................................. 234 14.3.5 Serial Mode Register (SMR) ................................................................................ 235 14.3.6 Serial Control Register (SCR) .............................................................................. 237 14.3.7 Serial Status Register (SSR) ................................................................................. 240 14.3.8 Bit Rate Register (BRR) ....................................................................................... 243 14.3.9 Serial Port Control Register (SPCR)..................................................................... 251 14.3.10 IrDA Control Register (IrCR)............................................................................... 252 14.3.11 Serial Extended Mode Register (SEMR) .............................................................. 253 Operation in Asynchronous Mode ..................................................................................... 253 14.4.1 Clock..................................................................................................................... 254 14.4.2 SCI3 Initialization................................................................................................. 258 14.4.3 Data Transmission ................................................................................................ 259 14.4.4 Serial Data Reception ........................................................................................... 261 Operation in Clock Synchronous Mode............................................................................. 265 14.5.1 Clock..................................................................................................................... 265 14.5.2 SCI3 Initialization................................................................................................. 265 14.5.3 Serial Data Transmission ...................................................................................... 266 14.5.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 268 14.5.5 Simultaneous Serial Data Transmission and Reception........................................ 270 IrDA Operation .................................................................................................................. 271 14.6.1 Transmission......................................................................................................... 272 14.6.2 Reception .............................................................................................................. 273 14.6.3 High-Level Pulse Width Selection........................................................................ 273 Interrupt Requests .............................................................................................................. 274 Usage Notes ....................................................................................................................... 277 14.8.1 Break Detection and Processing ........................................................................... 277 14.8.2 Mark State and Break Sending ............................................................................. 277 14.8.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only) ......................................................................... 277 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ............................................................................................. 278 14.8.5 Note on Switching SCK3 Pin Function ................................................................ 279 14.8.6 Relation between Writing to TDR and Bit TDRE ................................................ 279 14.8.7 Relation between RDR Reading and bit RDRF.................................................... 280 14.8.8 Transmit and Receive Operations when Making State Transition........................ 281 14.8.9 Setting in Subactive or Subsleep Mode ................................................................ 281 14.8.10 Oscillator when Serial Communication Interface 3 is Used ................................. 281
Rev. 3.00 May 15, 2007 Page xvi of xxxii
Section 15 Synchronous Serial Communication Unit (SSU) ............................283
15.1 Features.............................................................................................................................. 283 15.2 Input/Output Pins ............................................................................................................... 284 15.3 Register Descriptions ......................................................................................................... 285 15.3.1 SS Control Register H (SSCRH) .......................................................................... 285 15.3.2 SS Control Register L (SSCRL) ........................................................................... 287 15.3.3 SS Mode Register (SSMR) ................................................................................... 289 15.3.4 SS Enable Register (SSER) .................................................................................. 290 15.3.5 SS Status Register (SSSR) .................................................................................... 291 15.3.6 SS Receive Data Register (SSRDR) ..................................................................... 293 15.3.7 SS Transmit Data Register (SSTDR).................................................................... 293 15.3.8 SS Shift Register (SSTRSR)................................................................................. 293 15.4 Operation ........................................................................................................................... 293 15.4.1 Transfer Clock ...................................................................................................... 293 15.4.2 Relationship between Clock Polarity and Phase, and Data................................... 294 15.4.3 Relationship between Data Input/Output and Shift Register ................................ 295 15.4.4 Communication Modes and Pin Functions ........................................................... 296 15.4.5 Operation in Clocked Synchronous Communication Mode.................................. 297 15.4.6 Operation in Four-Line Bus Communication Mode ............................................. 303 15.4.7 Initialization in Four-Line Bus Communication Mode......................................... 304 15.4.8 Serial Data Transmission ...................................................................................... 305 15.4.9 Serial Data Reception ........................................................................................... 307 15.4.10 SCS Pin Control and Arbitration .......................................................................... 309 15.4.11 Interrupt Requests ................................................................................................. 310 15.5 Usage Note......................................................................................................................... 310
Section 16 I2C Bus Interface 2 (IIC2) ................................................................311
16.1 Features.............................................................................................................................. 311 16.2 Input/Output Pins ............................................................................................................... 313 16.3 Register Descriptions ......................................................................................................... 314 16.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 314 16.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 317 16.3.3 I2C Bus Mode Register (ICMR)............................................................................ 319 16.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 321 16.3.5 I2C Bus Status Register (ICSR)............................................................................. 323 16.3.6 Slave Address Register (SAR).............................................................................. 326 16.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 326 16.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 327 16.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 327
Rev. 3.00 May 15, 2007 Page xvii of xxxii
16.4 Operation ........................................................................................................................... 328 16.4.1 I2C Bus Format...................................................................................................... 328 16.4.2 Master Transmit Operation................................................................................... 329 16.4.3 Master Receive Operation .................................................................................... 331 16.4.4 Slave Transmit Operation ..................................................................................... 333 16.4.5 Slave Receive Operation....................................................................................... 336 16.4.6 Clock Synchronous Serial Format ........................................................................ 337 16.4.7 Noise Canceler...................................................................................................... 340 16.4.8 Example of Use..................................................................................................... 340 16.5 Interrupt Request................................................................................................................ 345 16.6 Bit Synchronous Circuit..................................................................................................... 346 16.7 Usage Notes ....................................................................................................................... 347 16.7.1 Note on Issuing Stop Condition and Start (Re-Transmit) Condition .................... 347 16.7.2 Note on Setting WAIT Bit in I2C Bus Mode Register (ICMR)............................ 347 16.7.3 Restriction on Transfer Rate Setting in Multimaster Operation ........................... 347 16.7.4 Restriction on the Use of Bit Manipulation Instructions for MST and TRS Setting in Multimaster Operation................................................................. 348 16.7.5 Usage Note on Master Receive Mode................................................................... 348
Section 17 A/D Converter ................................................................................. 349
17.1 Features.............................................................................................................................. 349 17.2 Input/Output Pins............................................................................................................... 350 17.3 Register Descriptions......................................................................................................... 350 17.3.1 A/D Result Register (ADRR) ............................................................................... 350 17.3.2 A/D Mode Register (AMR) .................................................................................. 351 17.3.3 A/D Start Register (ADSR) .................................................................................. 352 17.4 Operation ........................................................................................................................... 353 17.4.1 A/D Conversion .................................................................................................... 353 17.4.2 External Trigger Input Timing.............................................................................. 353 17.4.3 Operating States of A/D Converter....................................................................... 354 17.5 Example of Use.................................................................................................................. 354 17.6 A/D Conversion Accuracy Definitions .............................................................................. 357 17.7 Usage Notes ....................................................................................................................... 359 17.7.1 Permissible Signal Source Impedance .................................................................. 359 17.7.2 Influences on Absolute Accuracy ......................................................................... 359 17.7.3 Usage Notes .......................................................................................................... 360
Section 18 Comparators .................................................................................... 361
18.1 Features.............................................................................................................................. 361 18.2 Input/Output Pins............................................................................................................... 362
Rev. 3.00 May 15, 2007 Page xviii of xxxii
18.3 Register Descriptions ......................................................................................................... 362 18.3.1 Compare Control Registers 0, 1 (CMCR0, CMCR1) ........................................... 362 18.3.2 Compare Data Register (CMDR).......................................................................... 364 18.4 Operation ........................................................................................................................... 365 18.4.1 Operation Sequence .............................................................................................. 365 18.4.2 Hysteresis Characteristics of Comparator............................................................. 366 18.4.3 Interrupt Setting .................................................................................................... 366 18.5 Usage Notes ....................................................................................................................... 368
Section 19 Power-On Reset Circuit ...................................................................369
19.1 Feature ............................................................................................................................... 369 19.2 Operation ........................................................................................................................... 370 19.2.1 Power-On Reset Circuit ........................................................................................ 370
Section 20 List of Registers ...............................................................................371
20.1 Register Addresses (Address Order).................................................................................. 372 20.2 Register Bits....................................................................................................................... 376 20.3 Register States in Each Operating Mode ........................................................................... 380
Section 21 Electrical Characteristics .................................................................385
21.1 Absolute Maximum Ratings for F-ZTAT Version............................................................. 385 21.2 Electrical Characteristics for F-ZTAT Version.................................................................. 386 21.2.1 Power Supply Voltage and Operating Range........................................................ 386 21.2.2 DC Characteristics ................................................................................................ 393 21.2.3 AC Characteristics ................................................................................................ 399 21.2.4 A/D Converter Characteristics .............................................................................. 405 21.2.5 Comparator Characteristics................................................................................... 407 21.2.6 Watchdog Timer Characteristics........................................................................... 407 21.2.7 Power-On Reset Circuit Characteristics ............................................................... 408 21.2.8 Flash Memory Characteristics .............................................................................. 409 21.3 Absolute Maximum Ratings for Masked ROM Version.................................................... 411 21.4 Electrical Characteristics for Masked ROM Version......................................................... 412 21.4.1 Power Supply Voltage and Operating Range........................................................ 412 21.4.2 DC Characteristics ................................................................................................ 419 21.4.3 AC Characteristics ................................................................................................ 425 21.4.4 A/D Converter Characteristics .............................................................................. 431 21.4.5 Comparator Characteristics................................................................................... 433 21.4.6 Watchdog Timer Characteristics........................................................................... 433 21.4.7 Power-On Reset Circuit Characteristics ............................................................... 434 21.5 Operation Timing............................................................................................................... 435
Rev. 3.00 May 15, 2007 Page xix of xxxii
21.6 Output Load Circuit ........................................................................................................... 440 21.7 Recommended Resonators................................................................................................. 440 21.8 Usage Note......................................................................................................................... 441
Appendix
A.
......................................................................................................... 443
B.
C. D.
Instruction Set .................................................................................................................... 443 A.1 Instruction List...................................................................................................... 443 A.2 Operation Code Map............................................................................................. 458 A.3 Number of Execution States ................................................................................. 461 A.4 Combinations of Instructions and Addressing Modes .......................................... 472 I/O Ports............................................................................................................................. 473 B.1 I/O Port Block Diagrams ...................................................................................... 473 B.2 Port States in Each Operating State ...................................................................... 486 B.3 Port 9 Related Register Settings and Pin Functions.............................................. 487 Product Part No. Lineup .................................................................................................... 491 Package Dimensions .......................................................................................................... 492
Main Revisions and Additions in this Edition..................................................... 495 Index ......................................................................................................... 513
Rev. 3.00 May 15, 2007 Page xx of xxxii
Figures
Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Overview Internal Block Diagram of H8/38602R Group .............................................................. 2 Pin Assignment of H8/38602R Group (TNP-32) .......................................................... 3 Pin Assignment of H8/38602R Group (32P6U-A)........................................................ 3
Section 2 CPU Figure 2.1 Memory Map................................................................................................................. 8 Figure 2.2 CPU Registers ............................................................................................................... 9 Figure 2.3 Usage of General Registers ......................................................................................... 10 Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 11 Figure 2.5 General Register Data Formats (1).............................................................................. 13 Figure 2.5 General Register Data Formats (2).............................................................................. 14 Figure 2.6 Memory Data Formats................................................................................................. 15 Figure 2.7 Instruction Formats...................................................................................................... 26 Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 30 Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 32 Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 33 Figure 2.11 CPU Operating States................................................................................................ 34 Figure 2.12 State Transitions ........................................................................................................ 35 Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address ............................................................................................................ 36 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Exception Handling Reset Exception Handling Sequence........................................................................... 45 Block Diagram of Interrupt Controller........................................................................ 54 Flow up to Interrupt Acceptance ................................................................................. 55 Interrupt Exception Handling Sequence...................................................................... 56 Stack Status after Exception Handling ........................................................................ 57 Operation when Odd Address is Set in SP .................................................................. 58 PFCR and PMRB (or AEGSR) Setting and Interrupt Request Flag Clearing Procedure .............................................................................................. 59 Clock Pulse Generators Block Diagram of Clock Pulse Generators.................................................................. 63 Typical Connection to Crystal Resonator.................................................................... 66 Typical Connection to Ceramic Resonator.................................................................. 66 Example of External Clock Input ................................................................................ 67 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator................................ 68 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator.................................. 69
Rev. 3.00 May 15, 2007 Page xxi of xxxii
Figure 4.7 Pin Connection when not Using Subclock .................................................................. 69 Figure 4.8 Pin Connection when Inputting External Clock .......................................................... 70 Figure 4.9 Example of Crystal and Ceramic Resonator Assignment............................................ 72 Figure 4.10 Negative Resistance Measurement and Circuit Modification Suggestions ............... 73 Figure 4.11 Example of Incorrect Board Design .......................................................................... 74 Figure 4.12 Oscillation Stabilization Wait Time .......................................................................... 75 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Section 8 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Power-Down Modes Mode Transition Diagram ........................................................................................... 84 Standby Mode Transition and Pin States..................................................................... 97 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode ............................................................... 98 ROM Flash Memory Block Configuration.......................................................................... 100 Programming/Erasing Flowchart Example in User Program Mode.......................... 108 Program/Program-Verify Flowchart ......................................................................... 110 Erase/Erase-Verify Flowchart ................................................................................... 113 Module Standby Mode Setting.................................................................................. 116 I/O Ports Port 1 Pin Configuration............................................................................................ 119 Port 3 Pin Configuration............................................................................................ 124 Port 8 Pin Configuration............................................................................................ 128 Port 9 Pin Configuration............................................................................................ 132 Port B Pin Configuration........................................................................................... 138 Input/Output Data Inversion Function....................................................................... 142 Timer B1 Block Diagram of Timer B1...................................................................................... 145 Timer B1 Initial Setting Flow ................................................................................... 148 Processing Flow When Changing Setting during Counter Operation ....................... 149 Timer W Timer W Block Diagram......................................................................................... 155 Free-Running Counter Operation ............................................................................ 166 Periodic Counter Operation..................................................................................... 167 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 167 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 168 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 168 Input Capture Operating Example........................................................................... 169 Buffer Operation Example (Input Capture)............................................................. 170 PWM Mode Example (1) ........................................................................................ 171
Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 Figure 10.8 Figure 10.9
Rev. 3.00 May 15, 2007 Page xxii of xxxii
Figure 10.10 PWM Mode Example (2) ...................................................................................... 171 Figure 10.11 Buffer Operation Example (Output Compare) ...................................................... 172 Figure 10.12 PWM Mode Example (TOB, TOC, and TOD = 0: initial output values are set to 0)............................... 173 Figure 10.13 PWM Mode Example (TOB, TOC, and TOD = 1: initial output values are set to 1)............................... 174 Figure 10.14 Count Timing for Internal Clock Source ............................................................... 175 Figure 10.15 Count Timing for External Clock Source.............................................................. 175 Figure 10.16 Output Compare Output Timing ........................................................................... 176 Figure 10.17 Input Capture Input Signal Timing........................................................................ 177 Figure 10.18 Timing of Counter Clearing by Compare Match................................................... 177 Figure 10.19 Buffer Operation Timing (Compare Match).......................................................... 178 Figure 10.20 Buffer Operation Timing (Input Capture) ............................................................. 178 Figure 10.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 179 Figure 10.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 180 Figure 10.23 Timing of Status Flag Clearing by CPU................................................................ 180 Figure 10.24 Contention between TCNT Write and Clear ......................................................... 183 Figure 10.25 Internal Clock Switching and TCNT Operation.................................................... 183 Section 11 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Realtime Clock (RTC) Block Diagram of RTC ........................................................................................... 186 Definition of Time Expression ................................................................................ 191 Initial Setting Procedure .......................................................................................... 196 Example: Reading of Inaccurate Time Data............................................................ 197 Watchdog Timer Block Diagram of Watchdog Timer ........................................................................ 202 Example of Watchdog Timer Operation.................................................................. 208 Interval Timer Mode Operation............................................................................... 209 Timing of OVF Flag Setting.................................................................................... 209 Asynchronous Event Counter (AEC) Block Diagram of Asynchronous Event Counter .................................................... 214 Software Procedure when Using ECH and ECL as 16-Bit Event Counter.............. 223 Software Procedure when Using ECH and ECL as 8-Bit Event Counters .............. 224 Event Counter Operation Waveform....................................................................... 226 Example of Clock Control Operation...................................................................... 227
Section 14 Serial Communication Interface 3 (SCI3, IrDA) Figure 14.1 Block Diagram of SCI3 ........................................................................................... 232 Figure 14.2 Data Format in Asynchronous Communication ...................................................... 254
Rev. 3.00 May 15, 2007 Page xxiii of xxxii
Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............ 254 Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 258 Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)........................................................................... 259 Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 260 Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)........................................................................... 262 Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1) ..................... 263 Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2) ..................... 264 Figure 14.9 Data Format in Clock Synchronous Communication.............................................. 265 Figure 14.10 Example of SCI3 Operation in Transmission in Clock Synchronous Mode ..................................................................................... 266 Figure 14.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode) .................... 267 Figure 14.12 Example of SCI3 Reception Operation in Clock Synchronous Mode................... 268 Figure 14.13 Sample Serial Reception Flowchart (Clock Synchronous Mode) ......................... 269 Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clock Synchronous Mode) .................................................. 270 Figure 14.15 IrDA Block Diagram............................................................................................. 271 Figure 14.16 IrDA Transmission and Reception ........................................................................ 272 Figure 14.17 (a) RDRF Setting and RXI Interrupt ..................................................................... 276 Figure 14.17 (b) TDRE Setting and TXI Interrupt ..................................................................... 276 Figure 14.17 (c) TEND Setting and TEI Interrupt...................................................................... 276 Figure 14.18 Receive Data Sampling Timing in Asynchronous Mode ...................................... 278 Figure 14.19 Relation between RDR Read Timing and Data..................................................... 280 Section 15 Synchronous Serial Communication Unit (SSU) Figure 15.1 Block Diagram of SSU............................................................................................ 284 Figure 15.2 Relationship between Clock Polarity and Phase, and Data ..................................... 294 Figure 15.3 Relationship between Data Input/Output Pin and Shift Register ............................ 295 Figure 15.4 Initialization in Clocked Synchronous Communication Mode................................ 297 Figure 15.5 Example of Operation in Data Transmission .......................................................... 298 Figure 15.6 Sample Serial Transmission Flowchart ................................................................... 299 Figure 15.7 Example of Operation in Data Reception (MSS = 1) .............................................. 300 Figure 15.8 Sample Serial Reception Flowchart (MSS = 1)....................................................... 301 Figure 15.9 Sample Flowchart for Serial Transmit and Receive Operations.............................. 302 Figure 15.10 Initialization in Four-Line Bus Communication Mode ......................................... 304 Figure 15.11 Example of Operation in Data Transmission (MSS = 1)....................................... 306 Figure 15.12 Example of Operation in Data Reception (MSS = 1) ............................................ 308 Figure 15.13 Arbitration Check Timing ..................................................................................... 309
Rev. 3.00 May 15, 2007 Page xxiv of xxxii
Section 16 I2C Bus Interface 2 (IIC2) Figure 16.1 Block Diagram of I2C Bus Interface 2..................................................................... 312 Figure 16.2 External Circuit Connections of I/O Pins ................................................................ 313 Figure 16.3 I2C Bus Formats ...................................................................................................... 328 Figure 16.4 I2C Bus Timing........................................................................................................ 328 Figure 16.5 Master Transmit Mode Operation Timing (1) ......................................................... 330 Figure 16.6 Master Transmit Mode Operation Timing (2) ......................................................... 330 Figure 16.7 Master Receive Mode Operation Timing (1)........................................................... 332 Figure 16.8 Master Receive Mode Operation Timing (2)........................................................... 333 Figure 16.9 Slave Transmit Mode Operation Timing (1) ........................................................... 334 Figure 16.10 Slave Transmit Mode Operation Timing (2) ......................................................... 335 Figure 16.11 Slave Receive Mode Operation Timing (1)........................................................... 336 Figure 16.12 Slave Receive Mode Operation Timing (2)........................................................... 337 Figure 16.13 Clock Synchronous Serial Transfer Format .......................................................... 337 Figure 16.14 Transmit Mode Operation Timing......................................................................... 338 Figure 16.15 Receive Mode Operation Timing .......................................................................... 339 Figure 16.16 Block Diagram of Noise Conceler......................................................................... 340 Figure 16.17 Sample Flowchart for Master Transmit Mode....................................................... 341 Figure 16.18 Sample Flowchart for Master Receive Mode ........................................................ 342 Figure 16.19 Sample Flowchart for Slave Transmit Mode......................................................... 343 Figure 16.20 Sample Flowchart for Slave Receive Mode .......................................................... 344 Figure 16.21 Timing of Bit Synchronous Circuit ....................................................................... 346 Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Figure 17.6 Figure 17.7 Figure 17.8 Section 18 Figure 18.1 Figure 18.2 Figure 18.3 Figure 18.4 A/D Converter Block Diagram of A/D Converter ........................................................................... 349 External Trigger Input Timing ................................................................................ 353 Example of A/D Conversion Operation .................................................................. 355 Flowchart of Procedure for Using A/D Converter (Polling by Software) ............... 356 Flowchart of Procedure for Using A/D Converter (Interrupts Used) ...................... 356 A/D Conversion Accuracy Definitions (1) .............................................................. 358 A/D Conversion Accuracy Definitions (2) .............................................................. 358 Example of Analog Input Circuit ............................................................................ 359 Comparators Block Diagram of Comparators............................................................................... 361 Hysteresis/Non-Hysteresis Selection by CDR......................................................... 366 Procedure for Setting Interrupt (1) .......................................................................... 367 Procedure for Setting Interrupt (2) .......................................................................... 368
Section 19 Power-On Reset Circuit Figure 19.1 Power-On Reset Circuit........................................................................................... 369 Figure 19.2 Power-On Reset Circuit Operation Timing ............................................................. 370
Rev. 3.00 May 15, 2007 Page xxv of xxxii
Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6
Electrical Characteristics Power Supply Voltage and Oscillation Frequency Range (1) ................................. 386 Power Supply Voltage and Oscillation Frequency Range (2) ................................. 387 Power Supply Voltage and Operating Frequency Range (1)................................... 388 Power Supply Voltage and Operating Frequency Range (2)................................... 389 Power Supply Voltage and Operating Frequency Range (3)................................... 390 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (1) ................................................................................................... 391 Figure 21.7 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (2) ................................................................................................... 392 Figure 21.8 Power Supply Voltage and Oscillation Frequency Range (1) ................................. 412 Figure 21.9 Power Supply Voltage and Oscillation Frequency Range (2) ................................. 413 Figure 21.10 Power Supply Voltage and Operating Frequency Range (1)................................. 414 Figure 21.11 Power Supply Voltage and Operating Frequency Range (2)................................. 415 Figure 21.12 Power Supply Voltage and Operating Frequency Range (3)................................. 416 Figure 21.13 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (1).................................................................................................. 417 Figure 21.14 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (2).................................................................................................. 418 Figure 21.15 Clock Input Timing ............................................................................................... 435 Figure 21.16 RES Low Width Timing........................................................................................ 435 Figure 21.17 Input Timing.......................................................................................................... 435 Figure 21.18 SCK3 Input Clock Timing .................................................................................... 435 Figure 21.19 SCI3 Input/Output Timing in Clock Synchronous Mode...................................... 436 Figure 21.20 SSU Input/Output Timing in Clock Synchronous Mode....................................... 436 Figure 21.21 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 1) ................................. 437 Figure 21.22 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 0) ................................. 437 Figure 21.23 SSU Input/Output Timing (Four-Line Bus Communication Mode, Slave, CPHS = 1) ................................... 438 Figure 21.24 SSU Input/Output Timing (Four-Line Bus Communication Mode, Slave, CPHS = 0) ................................... 438 Figure 21.25 I2C Bus Interface Input/Output Timing ................................................................. 439 Figure 21.26 Power-On Reset Circuit Reset Timing .................................................................. 439 Figure 21.27 Output Load Condition.......................................................................................... 440 Figure 21.28 Recommended Resonators .................................................................................... 440 Appendix Figure B.1 (a) Port 1 Block Diagram (P12)................................................................................ 473 Figure B.1 (b) Port 1 Block Diagram (P11)................................................................................ 474
Rev. 3.00 May 15, 2007 Page xxvi of xxxii
Figure B.1 (c) Port 1 Block Diagram (P10)................................................................................ 475 Figure B.2 (a) Port 3 Block Diagram (P32)................................................................................ 476 Figure B.2 (b) Port 3 Block Diagram (P31)................................................................................ 477 Figure B.2 (c) Port 3 Block Diagram (P30)................................................................................ 478 Figure B.3 (a) Port 8 Block Diagram (P84 to P82)..................................................................... 479 Figure B.4 (a) Port 9 Block Diagram (P93)................................................................................ 480 Figure B.4 (b) Port 9 Block Diagram (P92)................................................................................ 481 Figure B.4 (c) Port 9 Block Diagram (P91)................................................................................ 482 Figure B.4 (d) Port 9 Block Diagram (P90)................................................................................ 483 Figure B.5 (a) Port B Block Diagram (PB5 or PB4) .................................................................. 484 Figure B.5 (b) Port B Block Diagram (PB3 or PB2) .................................................................. 484 Figure B.5 (c) Port B Block Diagram (PB1 or PB0) .................................................................. 485 Figure D.1 Package Dimensions (TNP-32) ................................................................................ 492 Figure D.2 Package Dimensions (32P6U-A).............................................................................. 493
Rev. 3.00 May 15, 2007 Page xxvii of xxxii
Rev. 3.00 May 15, 2007 Page xxviii of xxxii
Tables
Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 4 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 16 Table 2.2 Data Transfer Instructions....................................................................................... 17 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 18 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 19 Table 2.4 Logic Operations Instructions................................................................................. 20 Table 2.5 Shift Instructions..................................................................................................... 20 Table 2.6 Bit Manipulation Instructions (1)............................................................................ 21 Table 2.6 Bit Manipulation Instructions (2)............................................................................ 22 Table 2.7 Branch Instructions ................................................................................................. 23 Table 2.8 System Control Instructions.................................................................................... 24 Table 2.9 Block Data Transfer Instructions ............................................................................ 25 Table 2.10 Addressing Modes .................................................................................................. 27 Table 2.11 Absolute Address Access Ranges ........................................................................... 29 Table 2.12 Effective Address Calculation (1)........................................................................... 30 Table 2.12 Effective Address Calculation (2)........................................................................... 31 Section 3 Exception Handling Table 3.1 Exception Sources and Vector Address .................................................................. 42 Table 3.2 Reset Sources.......................................................................................................... 44 Table 3.3 Pin Configuration.................................................................................................... 46 Table 3.4 Interrupt Wait States ............................................................................................... 57 Section 4 Clock Pulse Generators Table 4.1 Methods for Selecting System Clock Oscillator and On-Chip Oscillator............... 67 Section 5 Power-Down Modes Table 5.1 Operating Frequency and Waiting Time................................................................. 79 Table 5.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 85 Table 5.3 Internal State in Each Operating Mode................................................................... 86 Section 6 ROM Table 6.1 Setting Programming Modes ................................................................................ 104 Table 6.2 Boot Mode Operation ........................................................................................... 107 Table 6.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible......................................................................................... 108 Table 6.4 Reprogramming Data Computation Table ............................................................ 111
Rev. 3.00 May 15, 2007 Page xxix of xxxii
Table 6.5 Table 6.6 Table 6.7
Additional-Program Data Computation Table ...................................................... 111 Programming Time ............................................................................................... 111 Flash Memory Operating States............................................................................ 115
Section 9 Timer B1 Table 9.1 Timer B1 Operating Modes .................................................................................. 151 Section 10 Timer W Table 10.1 Timer W Functions ............................................................................................... 154 Table 10.2 Pin Configuration.................................................................................................. 156 Table 10.3 Timer W Operating Modes ................................................................................... 181 Section 11 Realtime Clock (RTC) Table 11.1 Pin Configuration.................................................................................................. 186 Table 11.2 Interrupt Sources................................................................................................... 198 Section 12 Watchdog Timer Table 12.1 Assembly Program for Clearing WT/IT or IEOVF Bit to 0 ................................. 211 Table 12.2 The Value of "xx" ................................................................................................. 211 Section 13 Asynchronous Event Counter (AEC) Table 13.1 Pin Configuration.................................................................................................. 215 Table 13.2 Examples of Event Counter PWM Operation....................................................... 226 Table 13.3 Operating States of Asynchronous Event Counter................................................ 228 Table 13.4 Maximum Clock Frequency ................................................................................. 229 Section 14 Serial Communication Interface 3 (SCI3, IrDA) Table 14.1 Pin Configuration.................................................................................................. 233 Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 0) (1) ..................................................... 244 Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 0) (2) ..................................................... 244 Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 0) (3) ..................................................... 245 Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 0) (4) ..................................................... 245 Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 1) (1) ..................................................... 246 Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 1) (2) ..................................................... 246 Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 1) (3) ..................................................... 247
Rev. 3.00 May 15, 2007 Page xxx of xxxii
Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 1) (4)...................................................... 247 Relation between n and Clock .............................................................................. 248 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 248 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1) ................... 249 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2) ................... 250 Relation between n and Clock .............................................................................. 250 Data Transfer Formats (Asynchronous Mode)...................................................... 255 SMR Settings and Corresponding Data Transfer Formats.................................... 256 SMR and SCR Settings and Clock Source Selection............................................ 257 SSR Status Flags and Receive Data Handling...................................................... 262 IrCKS2 to IrCKS0 Bit Settings............................................................................. 273 SCI3 Interrupt Requests........................................................................................ 274 Transmit/Receive Interrupts ................................................................................. 275
Section 15 Synchronous Serial Communication Unit (SSU) Table 15.1 Pin Configuration.................................................................................................. 284 Table 15.2 Relationship between Communication Modes and Input/Output Pins.................. 296 Table 15.3 Interrupt Requests ................................................................................................. 310 Section 16 I2C Bus Interface 2 (IIC2) Table 16.1 Pin Configuration.................................................................................................. 313 Table 16.2 Transfer Rate ........................................................................................................ 316 Table 16.3 Interrupt Requests ................................................................................................. 345 Table 16.4 Time for Monitoring SCL..................................................................................... 346 Section 17 A/D Converter Table 17.1 Pin Configuration.................................................................................................. 350 Table 17.2 Operating States of A/D Converter....................................................................... 354 Section 18 Comparators Table 18.1 Pin Configuration.................................................................................................. 362 Table 18.2 Combination of CMR and CMLS Bits ................................................................. 364 Section 21 Electrical Characteristics Table 21.1 Absolute Maximum Ratings ................................................................................. 385 Table 21.2 DC Characteristics ................................................................................................ 393 Table 21.3 Control Signal Timing .......................................................................................... 399 Table 21.4 Serial Interface Timing ......................................................................................... 402 Table 21.5 Synchronous Serial Communication Unit (SSU) Timing ..................................... 403 Table 21.6 I2C Bus Interface Timing ...................................................................................... 404 Table 21.7 A/D Converter Characteristics .............................................................................. 405 Table 21.8 Comparator Characteristics................................................................................... 407
Rev. 3.00 May 15, 2007 Page xxxi of xxxii
Table 21.9 Table 21.10 Table 21.11 Table 21.12 Table 21.13 Table 21.14 Table 21.15 Table 21.16 Table 21.17 Table 21.18 Table 21.19 Table 21.20 Table 21.21 Appendix Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5 Table B.1
Watchdog Timer Characteristics........................................................................... 407 Power-On Reset Circuit Characteristics ............................................................... 408 Flash Memory Characteristics .............................................................................. 409 Absolute Maximum Ratings ................................................................................. 411 DC Characteristics ................................................................................................ 419 Control Signal Timing .......................................................................................... 425 Serial Interface Timing ......................................................................................... 428 Synchronous Serial Communication Unit (SSU) Timing ..................................... 429 I2C Bus Interface Timing...................................................................................... 430 A/D Converter Characteristics.............................................................................. 431 Comparator Characteristics................................................................................... 433 Watchdog Timer Characteristics........................................................................... 433 Power-On Reset Circuit Characteristics ............................................................... 434 Instruction Set....................................................................................................... 445 Operation Code Map (1) ....................................................................................... 458 Operation Code Map (2) ....................................................................................... 459 Operation Code Map (3) ....................................................................................... 460 Number of Cycles in Each Instruction.................................................................. 462 Number of Cycles in Each Instruction.................................................................. 463 Combinations of Instructions and Addressing Modes .......................................... 472 Port 9 Related Register Settings and Pin Functions.............................................. 487
Rev. 3.00 May 15, 2007 Page xxxii of xxxii
Section 1 Overview
Section 1 Overview
1.1 Features
* High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions * Various peripheral functions RTC (can be used as a free-running counter) Asynchronous event counter (AEC) Timer B1 Timer W Watchdog timer SCI (asynchronous or clock synchronous serial communication interface) SSU (synchronous serial communication unit)* I2C bus interface (conforms to the I2C bus interface format that is advocated by Philips Electronics)* 10-bit A/D converter Comparators Note: * SSU and IIC2 are shared. * On-chip memory
Product Classification Flash memory version TM (F-ZTAT version) Masked ROM version H8/38602RF H8/38602R H8/38600R Model HD64F38602R HD64338602R HD64338600R ROM 16 Kbytes 16 Kbytes 8 Kbytes RAM 1 Kbyte 1 Kbyte 512 bytes
Note: F-ZTATTM is a trademark of Renesas Technology Corp.
* General I/O ports I/O pins: 13 I/O pins, including three large current ports (IOL = 15 mA, @VOL = 1.0 V) Input-only pins: 6 input pins (also used as analog input pins) * Supports various power-down states
Rev. 3.00 May 15, 2007 Page 1 of 516 REJ09B0152-0300
Section 1 Overview
* Compact package
Package P-VQFN-32 P-LQFP-32 Code TNP-32 32P6U-A Body Size 5 x 6 mm 7 x 7 mm Pin Pitch 0.5 mm 0.8 mm Remarks
1.2
E7_0 E7_1 E7_2
Internal Block Diagram
X1 Vcc AVcc Vss RES TEST/ADTRG NMI*1
Subclock oscillator
X2 OSC1
H8/300H CPU
System clock oscillator
OSC2
RAM
Port 1
Watchdog timer
Realtime clock
P30/SCK3/VCref (/IRQ0) P31/RXD3/IrRXD P32/TXD3/IrTXD
Port 3
10-bit A/D converter
Comparators
SCI3/IrDA
I2C bus interface 2 *2
Notes: 1. The NMI pin is not available when the E7 or on-chip emulator debugger is used. 2. SSU and IIC2 are shared.
Figure 1.1 Internal Block Diagram of H8/38602R Group
Rev. 3.00 May 15, 2007 Page 2 of 516 REJ09B0152-0300
Port B
Asynchronous event counter
Port 9
Timer B1
Timer W
Port 8
P10/AEVH/FTIOA/TMOW/CLKOUT P11/AEVL/FTCI (/IRQ1) P12/IRQAEC/AECPWM
ROM
Power-on reset circuit
P82/FTIOB P83/FTIOC P84/FTIOD
P90/SCS/SCL P91/SSCK/SDA P92/SSO (/IRQ0) P93/SSI (/IRQ1)
SSU*2
PB0/AN0/IRQ0 PB1/AN1/IRQ1 PB2/AN2 PB3/AN3 PB4/AN4/COMP0 PB5/AN5/COMP1
Section 1 Overview
1.3
Pin Assignment
P31/RXD3/IrRXD P32/TXD3/IrTXD P93/SSI (/IRQ1) P92/SSO (/IRQ0) P91/SSCK/SDA
P90/SCS/SCL
E7_0 19
E7_1 18
25
24
23
22
21
20
17
E7_2
P30/SCK3/VCref (/IRQ0) PB5/AN5/COMP1 PB4/AN4/COMP0 PB3/AN3 PB2/AN2 PB1/AN1/IRQ1 PB0/AN0/IRQ0
26 27 28 29 30 31 32 TNP-32 (Top view)
16 15 14 13 12 11 10
NMI P12/IRQAEC/AECPWM P11/AEVL/FTCI (/IRQ1) P10/AEVH/FTIOA/TMOW/CLKOUT P82/FTIOB P83/FTIOC P84/FTIOD
1
2
3
4
5
6
7 OSC1
E7_0 19
8
E7_1 18
OSC2
AVcc
RES
VSS
X1
X2
Figure 1.2 Pin Assignment of H8/38602R Group (TNP-32)
P32/TXD3/IrTXD P93/SSI (/IRQ1) P92/SSO (/IRQ0)
P91/SSCK/SDA
P90/SCS/SCL
24
23
22
21
20
17
E7_2
TEST/ADTRG
Vcc
9
P31/RXD3/IrRXD P30/SCK3/VCref (/IRQ0) PB5/AN5/COMP1 PB4/AN4/COMP0 PB3/AN3 PB2/AN2 PB1/AN1/IRQ1 PB0/AN0/IRQ0
25 26 27 28 29 30 31 32 32P6U-A (Top view)
16 15 14 13 12 11 10 9
NMI P12/IRQAEC/AECPWM P11/AEVL/FTCI (/IRQ1) P10/AEVH/FTIOA/TMOW/CLKOUT P82/FTIOB P83/FTIOC P84/FTIOD TEST/ADTRG
1
2
3
4
5
6 VSS
7 OSC1
RES
OSC2
AVcc
Figure 1.3 Pin Assignment of H8/38602R Group (32P6U-A)
Vcc
X1
X2
8
Rev. 3.00 May 15, 2007 Page 3 of 516 REJ09B0152-0300
Section 1 Overview
1.4
Table 1.1
Type
Pin Functions
Pin Functions
Symbol Vcc Vss AVcc Pin No. I/O 8 6 1 Input Input Input Functions Power supply pin. Connect this pin to the system power supply. Ground pin. Connect this pin to the system power supply (0 V). Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. These pins connect with crystal or ceramic resonator for the system clock, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection. X1 X2 CLKOUT 2 3 13 4 Input Output Output Input These pins connect with a 32.768- or 38.4-kHz crystal resonator for the subclock. See section 4, Clock Pulse Generators, for a typical connection. Clock output pin. Reset pins. The power-on reset circuit is incorporated. When externally driven low, the chip is reset. Test pins. Also used as the ADTRG pin. When this pin is not used as the ADTRG pin, users cannot use this pin. Connect this pin to Vss. When this pin is used as the ADTRG pin, see section 17.4.2, External Trigger Input Timing.
Power supply pins
Clock pins
OSC1 OSC2
7 5
Input Output
System control
RES
TEST
9
Input
Rev. 3.00 May 15, 2007 Page 4 of 516 REJ09B0152-0300
Section 1 Overview
Type
Symbol
Pin No. I/O 16 Input
Functions NMI interrupt request pin. Non-maskable interrupt request input pin. In the F-ZTAT version, the level on this pin determines whether to enter the user or boot mode when the reset state is released. To enter the user mode, pull up this pin to the Vcc level.
Interrupt pins NMI
IRQ0 IRQ1 IRQAEC
32 Input (22, 26) 31 Input (14, 23) 15 Input
External interrupt request input pins. Can select the rising or falling edge.
Interrupt input pin for the asynchronous event counter. This pin enables the asynchronous event input. External event input pin. Output compare output/input capture input/PWM output pins. Event input pins for input to the asynchronous event counter. PWM output pin for the AEC. Divided clock output pin for the RTC. SCI3 clock I/O pin. SCI3 data input pins or data input pins for the IrDA format. SCI3 data output pins or data output pins for the IrDA format. SSU chip select I/O pin. SSU clock I/O pin. SSU transmit/receive data I/O pins.
Timer W
FTCI FTIOA to FTIOD
14 13 to 10 14 13 15 13 26 25 24 20 21 23 22 21 20
Input I/O Input Input Output Output I/O Input Output I/O I/O I/O I/O I/O I/O
Asynchronous event counter (AEC) RTC Serial communication interface 3 (SCI3) Synchronous serial communication unit (SSU) I C bus interface 2 (IIC2)
2
AEVL AEVH AECPWM TMOW SCK3 RXD3/ IrRXD TXD3/ IrTXD SCS SSCK SSI SSO SDA SCL
IIC data I/O pin. IIC clock I/O pin.
Rev. 3.00 May 15, 2007 Page 5 of 516 REJ09B0152-0300
Section 1 Overview
Type A/D converter
Symbol AN0 to AN5 ADTRG
Pin No. I/O 32 to 27 9 28 27 26 Input I/O Input Input Input
Functions Analog data input pins for the A/D converter. External trigger input pin for the A/D converter. Analog data input pins for the comparator. Reference voltage pin for external input of threshold voltage of the comparator analog input pins. 3-bit I/O pins. Input or output can be designated for each bit by means of the port control register 1 (PCR1). 3-bit I/O pins. Input or output can be designated for each bit by means of the port control register 3 (PCR3). 3-bit I/O pins. Input or output can be designated for each bit by means of the port control register 8 (PCR8). 4-bit I/O pins. Input or output can be designated for each bit by means of the port control register 9 (PCR9). 6-bit input-only pins. E7 emulator interface pins. E7_2 selects whether the on-chip oscillator is used. E7_2 is pulled up or down by a 100-k resistance. For details, see section 4, Clock Pulse Generators.
Comparators COMP0 COMP1 VCref I/O ports
P10 to P12 13 to 15 P30 to P32 26 to 24 P82 to P84 12 to 10 P90 to P93 20 to 23 PB0 to PB5 32 to 27
I/O
I/O
I/O
Input
E7
E7_0 E7_1 E7_2
19 to 17
Rev. 3.00 May 15, 2007 Page 6 of 516 REJ09B0152-0300
Section 2 CPU
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward compatible with the H8/300 CPU, and supports only normal mode, which has a 64-Kbyte address space. * Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added. * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers, or eight 32-bit registers * Sixty-two basic instructions 8/16/32-bit data transfer and arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 64-Kbyte address space * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 2 states 8 x 8-bit register-register multiply: 14 states 16 / 8-bit register-register divide: 14 states 16 x 16-bit register-register multiply: 22 states 32 / 16-bit register-register divide: 22 states
CPU30H2C_000120030300
Rev. 3.00 May 15, 2007 Page 7 of 516 REJ09B0152-0300
Section 2 CPU
* Power-down state Transition to power-down state by SLEEP instruction
2.1
Address Space and Memory Map
The address space of this LSI is 64 Kbytes, which includes the program area and the data area. Figure 2.1 shows the memory map.
HD64F38602R
(Flash memory version)
HD64338602R
(Masked ROM version)
HD64338600R
(Masked ROM version)
H'0000 H'0050
Interrupt vector
On-chip ROM (16 Kbytes)
H'0000 H'0050
Interrupt vector
On-chip ROM (16 Kbytes)
H'0000 H'0050
Interrupt vector On-chip ROM (8 Kbytes)
H'1FFF
H'3FFF
H'3FFF
Not used
Not used
Not used
H'F020
Internal I/O registers
H'F020
Internal I/O registers
H'F020
Internal I/O registers
H'F100
H'F100
H'F100
Not used
Not used
Not used
H'FB80
On-chip RAM (1 Kbyte)
H'FB80
On-chip RAM (1 Kbyte)
H'FD80 H'FF80
H'FF80
Internal I/O registers
H'FF80
Internal I/O registers
On-chip RAM (512 bytes) Internal I/O registers
H'FFFF
H'FFFF
H'FFFF
Figure 2.1 Memory Map
Rev. 3.00 May 15, 2007 Page 8 of 516 REJ09B0152-0300
Section 2 CPU
2.2
Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
General Registers (ERn)
15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0
Control Registers (CR)
23 PC 0
76543210
CCR I UI H U N Z V C
[Legend]
SP: PC: CCR: I: UI: Stack pointer Program counter Condition-code register Interrupt mask bit User bit H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag
Figure 2.2 CPU Registers
Rev. 3.00 May 15, 2007 Page 9 of 516 REJ09B0152-0300
Section 2 CPU
2.2.1
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. The usage of each register can be selected independently.
* Address registers * 32-bit registers * 16-bit registers E registers (extended registers) (E0 to E7) RH registers (R0H to R7H) R registers (R0 to R7) RL registers (R0L to R7L) * 8-bit registers
ER registers (ER0 to ER7)
Figure 2.3 Usage of General Registers
Rev. 3.00 May 15, 2007 Page 10 of 516 REJ09B0152-0300
Section 2 CPU
General register ER7 has the function of the stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between the stack pointer and the stack area.
Empty area SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the start address is loaded by the vector address generated during reset exception-handling sequence. 2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
Rev. 3.00 May 15, 2007 Page 11 of 516 REJ09B0152-0300
Section 2 CPU
Bit 7
Bit Name I
Initial Value 1
R/W R/W
Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Negative Flag Stores the value of the most significant bit of data as a sign bit. Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry
6
UI
Undefined R/W
5
H
Undefined R/W
4
U
Undefined R/W
3
N
Undefined R/W
2
Z
Undefined R/W
1
V
Undefined R/W
0
C
Undefined R/W
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Rev. 3.00 May 15, 2007 Page 12 of 516 REJ09B0152-0300
Section 2 CPU
2.3
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type
1-bit data
General Register
RnH
Data Format
7 0 Don't care
7
0
76 54 32 10
1-bit data
RnL
Don't care
76 54 32 10
7
4-bit BCD data RnH Upper
43
Lower
0
Don't care
7
4-bit BCD data RnL
43
Upper Lower
0
Don't care
7
Byte data RnH
0
Don't care
MSB
LSB
7
Byte data RnL
0 LSB
Don't care
MSB
Figure 2.5 General Register Data Formats (1)
Rev. 3.00 May 15, 2007 Page 13 of 516 REJ09B0152-0300
Section 2 CPU
Data Type Word data
General Register Rn
Data Format
15
0
Word data
En
15 0
MSB
LSB
MSB
LSB
16 15
0
Longword data
ERn
31
MSB
LSB
[Legend]
ERn: General register ER En: Rn: General register E General register R
RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit
Figure 2.5 General Register Data Formats (2)
Rev. 3.00 May 15, 2007 Page 14 of 516 REJ09B0152-0300
Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 (SP) is used as an address register to access the stack area, the operand size should be word or longword.
Data Type Address
7 1-bit data Address L 7 6 5 4 3 2 1
Data Format
0 0
Byte data
Address L
MSB
LSB
Word data
Address 2M Address 2M+1
MSB LSB
Longword data
Address 2N Address 2N+1 Address 2N+2 Address 2N+3
MSB
LSB
Figure 2.6 Memory Data Formats
Rev. 3.00 May 15, 2007 Page 15 of 516 REJ09B0152-0300
Section 2 CPU
2.4
2.4.1
Instruction Set
Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1
Symbol Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / :3/:8/:16/:24 Note: *
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) 3-, 8-, 16-, or 24-bit length
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
Rev. 3.00 May 15, 2007 Page 16 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.2
Instruction MOV
Data Transfer Instructions
Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) Rd Cannot be used in this LSI. Rs (EAs) Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP.
MOVFPE MOVTPE POP
B B W/L
PUSH
W/L
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
Rev. 3.00 May 15, 2007 Page 17 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.3
Instruction ADD SUB
Arithmetic Operations Instructions (1)
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU
B
B/W/L
L B
B/W
MULXS
B/W
DIVXU
B/W
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
Rev. 3.00 May 15, 2007 Page 18 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.3
Instruction DIVXS
Arithmetic Operations Instructions (2)
Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit.
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
Rev. 3.00 May 15, 2007 Page 19 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.4
Instruction AND
Logic Operations Instructions
Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement (logical complement) of general register contents.
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
Note:
* Refers to the operand size. B: Byte W: Word L: Longword
Table 2.5
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note:
Shift Instructions
Size* B/W/L B/W/L B/W/L B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry flag.
* Refers to the operand size. B: Byte W: Word L: Longword
Rev. 3.00 May 15, 2007 Page 20 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.6
Instruction BSET
Bit Manipulation Instructions (1)
Size* B Function 1 ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. 0 ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) ( of ) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ( of ) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BCLR
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
BIOR
B
Note:
* Refers to the operand size. B: Byte
Rev. 3.00 May 15, 2007 Page 21 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.6
Instruction BXOR
Bit Manipulation Instructions (2)
Size* B Function C ( of ) C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ( of ) C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. ( of ) C Transfers a specified bit in a general register or memory operand to the carry flag. ( of ) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) Transfers the carry flag value to a specified bit in a general register or memory operand. C ( of ) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data.
BIXOR
B
BLD
B
BILD
B
BST
B
BIST
B
Note:
* Refers to the operand size. B: Byte
Rev. 3.00 May 15, 2007 Page 22 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.7
Instruction Bcc*
Branch Instructions
Size Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1
JMP BSR JSR RTS Note: *

Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine
Bcc is the general name for conditional branch instructions.
Rev. 3.00 May 15, 2007 Page 23 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.8
Instruction TRAPA RTE SLEEP LDC
System Control Instructions
Size* B/W Function Starts trap-instruction exception handling Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. CCR #IMM CCR Logically ANDs the CCR with immediate data. CCR #IMM CCR Logically ORs the CCR with immediate data. CCR #IMM CCR Logically XORs the CCR with immediate data. PC + 2 PC Only increments the program counter.
STC
B/W
ANDC ORC XORC NOP Note:
B B B
* Refers to the operand size. B: Byte W: Word
Rev. 3.00 May 15, 2007 Page 24 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.9
Instruction EEPMOV.B
Block Data Transfer Instructions
Size Function if R4L 0 then Repeat @ER5+ @ER6+, R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+, R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed.
EEPMOV.W
Rev. 3.00 May 15, 2007 Page 25 of 516 REJ09B0152-0300
Section 2 CPU
2.4.2
Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00). * Condition Field Specifies the branching condition of Bcc instructions.
(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA(disp) rn rm MOV.B @(d:16, Rn), Rm
(4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:8
Figure 2.7 Instruction Formats
Rev. 3.00 May 15, 2007 Page 26 of 516 REJ09B0152-0300
Section 2 CPU
2.5
Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode (@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.10 Addressing Modes
No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:24,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Rev. 3.00 May 15, 2007 Page 27 of 516 REJ09B0152-0300
Section 2 CPU
Register Direct--Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. Register Indirect with Displacement--@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added. Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. * Register indirect with pre-decrement@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even. Absolute Address--@aa:8, @aa:16, @aa:24 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits (@aa:8), 16 bits (@aa:16), or 24 bits (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space.
Rev. 3.00 May 15, 2007 Page 28 of 516 REJ09B0152-0300
Section 2 CPU
The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the upper 8 bits are ignored. Table 2.11 Absolute Address Access Ranges
Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) Access Range H'FF00 to H'FFFF H'0000 to H'FFFF H'0000 to H'FFFF
Immediate--#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF). Note that the first part of the address range is also the exception vector area.
Rev. 3.00 May 15, 2007 Page 29 of 516 REJ09B0152-0300
Section 2 CPU
Specified by @aa:8
Dummy Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode 2.5.2 Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1)
No 1
Addressing Mode and Instruction Format
Register direct(Rn)
Effective Address Calculation
Effective Address (EA)
Operand is general register contents.
op 2
rm
rn 31
General register contents
Register indirect(@ERn)
0
23
0
op 3
r
Register indirect with displacement @(d:16,ERn) or @(d:24,ERn)
31
General register contents
0 23 0
op
r
disp 31
Sign extension
0 disp
4
Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+
31
General register contents
0
23
0
op
r 31
1, 2, or 4
*Register indirect with pre-decrement @-ERn
0
General register contents
23
0
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the operand is byte size, 2 for word size, and 4 for longword size.
Rev. 3.00 May 15, 2007 Page 30 of 516 REJ09B0152-0300
Section 2 CPU
Table 2.12 Effective Address Calculation (2)
No 5
Addressing Mode and Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8 op abs
23 H'FFFF
87
0
@aa:16 op abs
23
16 15
0
Sign extension
@aa:24 op abs 23 0
6
Immediate
#xx:8/#xx:16/#xx:32 op IMM
Operand is immediate data.
7
Program-counter relative @(d:8,PC) @(d:16,PC)
23
PC contents
0
op
disp
23
Sign extension
0 disp 23 0
8
Memory indirect @@aa:8
23 op abs H'0000 15
87 abs
0
0
Memory contents
23
16 15 H'00
0
[Legend] r, rm,rn : op : disp : IMM : abs :
Register field Operation field Displacement Immediate data Absolute address
Rev. 3.00 May 15, 2007 Page 31 of 516 REJ09B0152-0300
Section 2 CPU
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock () or a subclock (SUB). The period from a rising edge of or SUB to the next rising edge is called one state. A bus cycle consists of two states. 2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle
T1 state
or SUB
T2 state
Internal address bus
Address
Internal read signal Internal data bus (read access)
Read data
Internal write signal
Internal data bus (write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
Rev. 3.00 May 15, 2007 Page 32 of 516 REJ09B0152-0300
Section 2 CPU
2.6.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 20.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral module.
Bus cycle
T1 state
or SUB
T2 state
T3 state
Internal address bus Internal read signal Internal data bus (read access) Internal write signal
Internal data bus (write access)
Address
Read data
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
Rev. 3.00 May 15, 2007 Page 33 of 516 REJ09B0152-0300
Section 2 CPU
2.7
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. For the program halt state, there are sleep (high-speed or medium-speed) mode, standby mode, watch mode, and subsleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 5, Power-Down Modes. For details on exception handling, refer to section 3, Exception Handling.
CPU state
Reset state The CPU is initialized Program execution state Active (high-speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock
Active (medium-speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock
Program halt state A state in which the CPU operation is stopped to reduce power consumption
Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode
Exception-handling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operating States
Rev. 3.00 May 15, 2007 Page 34 of 516 REJ09B0152-0300
Power-down modes
Section 2 CPU
Reset cleared Reset state
Reset occurs
Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Interrupt source
Exceptionhandling complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.12 State Transitions
2.8
2.8.1
Usage Notes
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4 or R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4, R4L, and R6 so that the end address of the destination address (value of R6 + R4L or R6 + R4) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution).
Rev. 3.00 May 15, 2007 Page 35 of 516 REJ09B0152-0300
Section 2 CPU
2.8.3
Bit-Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. Special care is required when using these instructions in cases where two registers are assigned to the same address, or when a bit is directly manipulated for a port or a register containing a write-only bit, because this may rewrite data of a bit other than the bit to be manipulated. Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address. When a bit-manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. Data is read in byte units. 2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction. 3. The written data is written again in byte units to the timer load register. The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register.
Read Count clock Timer counter
Reload Write Timer load register
Internal data bus
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address
Rev. 3.00 May 15, 2007 Page 36 of 516 REJ09B0152-0300
Section 2 CPU
Example 2: When the BSET instruction is executed for port 5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below. * Prior to executing BSET instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BSET instruction executed instruction BSET #0, @PDR5 The BSET instruction is executed for port 5.
* After executing BSET instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 0 P56 Input High level 0 1 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output High level 1 1
* Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40. 2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41. 3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
Rev. 3.00 May 15, 2007 Page 37 of 516 REJ09B0152-0300
Section 2 CPU
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR5. Prior to executing BSET instruction MOV.B MOV.B MOV.B #H'80, R0L R0L, @RAM0 R0L, @PDR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0
The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output Low level 1 0 0
* BSET instruction executed BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0).
* After executing BSET instruction MOV.B MOV.B @RAM0, R0L R0L, @PDR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 1 P56 Input High level 0 0 0
The work area (RAM0) value is written to PDR5.
P55 Output Low level 1 0 0
P54 Output Low level 1 0 0
P53 Output Low level 1 0 0
P52 Output Low level 1 0 0
P51 Output Low level 1 0 0
P50 Output High level 1 1 1
Rev. 3.00 May 15, 2007 Page 38 of 516 REJ09B0152-0300
Section 2 CPU
Bit Manipulation in a Register Containing a Write-Only Bit Example 3: BCLR instruction executed designating port 5 control register PCR5 P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin. * Prior to executing BCLR instruction
P57 Input/output Pin state PCR5 PDR5 Input Low level 0 1 P56 Input High level 0 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Output Low level 1 0
* BCLR instruction executed BCLR #0, @PCR5 The BCLR instruction is executed for PCR5.
* After executing BCLR instruction
P57 Input/output Pin state PCR5 PDR5 Output Low level 1 1 P56 Output High level 1 0 P55 Output Low level 1 0 P54 Output Low level 1 0 P53 Output Low level 1 0 P52 Output Low level 1 0 P51 Output Low level 1 0 P50 Input High level 0 0
* Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F. 2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. 3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent this problem, store a copy of the PDR5 data in a work area in memory and manipulate data of the bit in the work area, then write this data to PDR5.
Rev. 3.00 May 15, 2007 Page 39 of 516 REJ09B0152-0300
Section 2 CPU
* Prior to executing BCLR instruction MOV.B MOV.B MOV.B #H'3F, R0L R0L, @RAM0 R0L, @PCR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0
The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output Low level 1 0 1
* BCLR instruction executed BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0). * After executing BCLR instruction MOV.B MOV.B @RAM0, R0L R0L, @PCR5
P57 Input/output Pin state PCR5 PDR5 RAM0 Input Low level 0 1 0 P56 Input High level 0 0 0
The work area (RAM0) value is written to PCR5.
P55 Output Low level 1 0 1
P54 Output Low level 1 0 1
P53 Output Low level 1 0 1
P52 Output Low level 1 0 1
P51 Output Low level 1 0 1
P50 Output High level 0 0 0
Rev. 3.00 May 15, 2007 Page 40 of 516 REJ09B0152-0300
Section 3 Exception Handling
Section 3 Exception Handling
Exception handling is caused by a reset, a trap instruction (TRAPA), or interrupts. * Reset A reset has the highest exception priority. Exception handling starts after the reset state is cleared by a negation of the RES signal. Exception handling is also started when the watchdog timer overflows. The exception handling executed at this time is the same as that for a reset by the RES pin. * Trap Instruction Exception handling starts when a trap instruction (TRAPA) is executed. A vector address corresponding to a vector number from 0 to 3 which are specified in the instruction code is generated. Exception handling can be executed at all times in the program execution state, regardless of the setting of the I bit in CCR. * Interrupts External interrupts other than the NMI and internal interrupts are masked by the I bit in CCR, and kept pending while the I bit is set to 1. Exception handling starts when the current instruction or exception handling ends, if an interrupt is requested.
Rev. 3.00 May 15, 2007 Page 41 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.1 Exception Sources and Vector Address
Exception Sources Reset Reserved for system use NMI Trap instruction #0 Trap instruction #1 Trap instruction #2 Trap instruction #3 Reserved for system use Direct transition by executing the SLEEP instruction Reserved for system use IRQ0 IRQ1 IRQAEC Reserved for system use COMP0 COMP1 0.25-second overflow 0.5-second overflow Second periodic overflow Minute periodic overflow Hour periodic overflow Day-of-week periodic overflow Week periodic overflow Free-running overflow Vector Number 0 1 to 6 7 8 9 10 11 12 13 14, 15 16 17 18 19, 20 21 22 23 24 25 26 27 28 29 30 Vector Address H'0000 to H'0001 H'0002 to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'0032 to H'0033 H'0034 to H'0035 H'0036 to H'0037 H'0038 to H'0039 H'003A to H'003B H'003C to H'003D Low Priority High
Source Origin Reset pin/ watchdog timer External interrupt Trap instruction TRAPA #0 Trap instruction TRAPA #1 Trap instruction TRAPA #2 Trap instruction TRAPA #3 CPU External interrupts
Comparators RTC
Rev. 3.00 May 15, 2007 Page 42 of 516 REJ09B0152-0300
Section 3 Exception Handling
Source Origin WDT Asynchronous event counter Timer B1 Synchronous serial communication unit (SSU)/
Exception Sources WDT overflow (interval timer) Asynchronous event counter overflow Overflow Overrun error (SSU) Transmit data empty (SSU) Transmit end (SSU) Receive data full (SSU) Conflict error (SSU)/ Transmit data empty (IIC2) Transmit end (IIC2) Receive data full (IIC2) NACK detection (IIC2) Arbitration (IIC2) Overrun error (IIC2) Input capture A/compare match A Input capture B/compare match B Input capture C/compare match C Input capture D/compare match D Overflow Reserved for system use Transmit end Transmit data empty Receive data full Overrun error Framing error Parity error A/D conversion end Reserved for system use
Vector Number 31 32 33 34
Vector Address H'003E to H'003F H'0040 to H'0041 H'0042 to H'0043 H'0044 to H'0045
Priority High
IIC2*
Timer W
35
H'0046 to H'0047
SCI3
36 37
H'0048 to H'0049 H'004A to H'004B
A/D converter Note: *
38 39
H'004C to H'004D H'004E to H'004F Low
The SSU and IIC share the same vector address. When using the IIC, shift the SSU to standby mode using CKSTPR2.
Rev. 3.00 May 15, 2007 Page 43 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.2
Reset
A reset has the highest exception priority. There are three sources to generate a reset. Table 3.2 lists the reset sources. Table 3.2 Reset Sources
Description Low level input When the power supply voltage (Vcc) rises For details, see section 19, Power-On Reset Circuit. When the counter overflows For details, see section 12, Watchdog Timer.
Reset Source RES pin Power-on reset circuit Watchdog timer
3.2.1
Reset Exception Handling
When a reset source is generated, all the processing in execution is terminated and this LSI enters the reset state. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by a reset. To ensure that this LSI is reset, handle the RES pin as shown below. * When power is supplied, or the system clock oscillator is stopped Hold the RES pin low until oscillation of the system clock oscillator has stabilized. * When the system clock oscillator is operating Hold the RES pin low for the tREL state, which is specified as the electrical characteristics. After a reset source is generated, this LSI starts reset exception handling as follows. 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, and the I bit in CCR is set to 1. 2. The reset exception handling vector address (H'0000 and H'0001) is read and transferred to the PC, and then program execution starts from the address indicated by the PC. The reset exception handling sequence by the RES pin is shown in figure 3.1.
Rev. 3.00 May 15, 2007 Page 44 of 516 REJ09B0152-0300
Section 3 Exception Handling
Reset cleared Initial program instruction prefetch Vector fetch Internal processing RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction (2) (3) (1) (2)
Figure 3.1 Reset Exception Handling Sequence 3.2.2 Interrupt Immediately after Reset
Immediately after a reset, if an interrupt is accepted before the stack pointer (SP) is initialized, PC and CCR will not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.L #xx: 32, SP).
Rev. 3.00 May 15, 2007 Page 45 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.3
Input/Output Pins
Table 3.3 shows the pin configuration of the interrupt controller. Table 3.3
Name NMI IRQAEC IRQ1 IRQ0
Pin Configuration
I/O Input Input Input Input Function Nonmaskable external interrupt pin Rising or falling edge can be selected Maskable external interrupt pin Rising, falling, or both edges can be selected Maskable external interrupt pins Rising or falling edge can be selected
3.4
Register Descriptions
The interrupt controller has the following registers. * * * * * Interrupt edge select register (IEGR) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt flag register 1 (IRR1) Interrupt flag register 2 (IRR2)
Rev. 3.00 May 15, 2007 Page 46 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.4.1
Interrupt Edge Select Register (IEGR)
IEGR selects whether interrupt requests of the NMI, ADTRG, IRQ1, and IRQ0 pins are generated at the rising edge or falling edge.
Bit 7 Bit Name NMIEG Initial Value 0 R/W R/W Descriptions NMI Edge Select 0: Detects a falling edge of the NMI pin input 1: Detects a rising edge of the NMI pin input 6 5 0 R/W Reserved This bit is always read as 0. ADTRGNEG 0 ADTRG Edge Select 0: Detects a falling edge of the ADTRG pin input 1: Detects a rising edge of the ADTRG pin input 4 to 2 1 IEG1 All 0 0 R/W Reserved The write value should always be 0. IRQ1 Edge Select 0: Detects a falling edge of the IRQ1 pin input 1: Detects a rising edge of the IRQ1 pin input 0 IEG0 0 R/W IRQ0 Edge Select 0: Detects a falling edge of the IRQ0 pin input 1: Detects a rising edge of the IRQ0 pin input
Rev. 3.00 May 15, 2007 Page 47 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.4.2
Interrupt Enable Register 1 (IENR1)
IENR1 enables the RTC, IRQAEC, IRQ1, and IRQ0 interrupts.
Bit 7 Bit Name IENRTC Initial Value 0 R/W R/W Description RTC Interrupt Request Enable The RTC interrupt request is enabled when this bit is set to 1. 6 to 3 2 IENEC2 All 0 0 R/W Reserved The write value should always be 0. IRQAEC Interrupt Request Enable The IRQAEC interrupt request is enabled when this bit is set to 1. 1 IEN1 0 R/W IRQ1 Interrupt Request Enable The IRQ1 interrupt request is enabled when this bit is set to 1. 0 IEN0 0 R/W IRQ0 Interrupt Request Enable The IRQ0 interrupt request is enabled when this bit is set to 1.
Rev. 3.00 May 15, 2007 Page 48 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.4.3
Interrupt Enable Register 2 (IENR2)
IENR2 enables the A/D converter, timer B1, and asynchronous event counter interrupts.
Bit 7 6 Bit Name IENAD Initial Value 0 0 R/W R/W Description Reserved The write value should always be 0. A/D Converter Interrupt Request Enable The A/D converter interrupt request is enabled when this bit is set to 1. 5 to 3 2 IENTB1 All 0 0 R/W Reserved The write value should always be 0. Timer B1 Interrupt Request Enable The timer B1 interrupt request is enabled when this bit is set to 1. 1 0 IENEC 0 0 R/W Reserved The write value should always be 0. Asynchronous Event Counter Interrupt Request Enable The asynchronous event counter interrupt request is enabled when this bit is set to 1.
Rev. 3.00 May 15, 2007 Page 49 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.4.4
Interrupt Flag Register 1 (IRR1)
IRR1 indicates the IRQAEC, IRQ1, and IRQ0 interrupt request status.
Bit 7 to 3 2 Bit Name IRREC2 Initial Value All 0 0 R/W Description Reserved The write value should always be 0. R/(W)* IRQAEC Interrupt Request Flag [Setting condition] When the P12 pin is set to the IRQAEC/AECPWM pin and the specified edge is detected as the pin state [Clearing condition] When 0 is written to this bit 1 IRRI1 0 R/(W)* IRQ1 Interrupt Request Flag [Setting condition] When the IRQ1 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit 0 IRRI0 0 R/(W)* IRQ0 Interrupt Request Flag [Setting condition] When the IRQ0 pin is set as the interrupt input pin and the specified edge is detected [Clearing condition] When 0 is written to this bit Note: * Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 50 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.4.5
Interrupt Flag Register 2 (IRR2)
IRR2 indicates the interrupt request status of the A/D converter, timer B1, and asynchronous event counter.
Bit 7 6 Bit Name IRRAD Initial Value 0 0 R/W Description Reserved The write value should always be 0. R/(W)* A/D Converter Interrupt Request Flag [Setting condition] When A/D conversion ends [Clearing condition] When 0 is written to this bit 5 to 3 2 IRRTB1 All 0 0 Reserved The write value should always be 0. R/(W)* Timer B1 Interrupt Request Flag [Setting condition] When the timer B1 compare match or overflow occurs [Clearing condition] When 0 is written to this bit 1 0 IRREC 0 0 Reserved The write value should always be 0. R/(W)* Asynchronous Event Counter Interrupt Request Flag [Setting condition] When the asynchronous event counter overflows [Clearing condition] When 0 is written to this bit Note: * Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 51 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.5
3.5.1
Interrupt Sources
External Interrupts
There are four external interrupts: NMI, IRQAEC, IRQ1, and IRQ0. (1) NMI Interrupt
NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the state of the I bit in CCR. The NMIEG bit in IEGR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. (2) IRQ1 and IRQ0 Interrupts
IRQ1 and IRQ0 interrupts are requested by input signals at IRQ1 and IRQ0 pins. Using the IEG1 and IEG0 bits in IEGR, it is possible to select whether an interrupt is generated by a rising or falling edge at IRQ1 and IRQ0 pins. When the specified edge is input while the IRQ1 and IRQ0 pin functions are selected by PFCR and PMRB, the corresponding bit in IRR1 is set to 1 and an interrupt request is generated. Clearing the IEN1 and IEN0 bits in IENR1 to 0 disables the interrupt request to be accepted. Setting the I bit in CCR to 1 masks all interrupts. (3) IRQAEC Interrupts
An IRQAEC interrupt is requested by an input signal at the IRQAEC pin or IECPWM (PWM output for the AEC). When the IRQAEC pin is used as an external interrupt pin, clear the ECPWME bit in AEGSR to 0. Using the AIEGS1 and AIEGS0 bits in AEGSR, it is possible to select whether an interrupt is generated by a rising edge, falling edge, or both edges. When the IENEC2 bit in IENR1 is set to 1 and the specified edge is input, the corresponding bit in IRR1 is set to 1 and an interrupt request is generated. For details, see section 13, Asynchronous Event Counter (AEC).
Rev. 3.00 May 15, 2007 Page 52 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.5.2
Internal Interrupts
Internal interrupts generated from the on-chip peripheral modules have the following features: * For each on-chip peripheral module, there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. Internal interrupts can be controlled independently. If an enable bit is set to 1, an interrupt request is sent to the interrupt controller.
3.6
Operation
NMI interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts and on-chip peripheral module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. Interrupt operation is described as follows. 1. If an interrupt source whose interrupt enable register bit is set to 1 occurs, an interrupt request is sent to the interrupt controller. 2. When the interrupt controller receives an interrupt request, it sets the interrupt request flag. 3. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending (see table 3.1). 4. The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending. 5. If the interrupt request is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.5. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 6. The I bit of CCR is set to 1, masking further interrupts. 7. The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed.
Rev. 3.00 May 15, 2007 Page 53 of 516 REJ09B0152-0300
Section 3 Exception Handling
Interrpt controller
External or internal interrupts
Priority decision logic
Interrupt request
External interrupts or internal interrupt enable signals I CCR (CPU)
Figure 3.2 Block Diagram of Interrupt Controller
Rev. 3.00 May 15, 2007 Page 54 of 516 REJ09B0152-0300
Section 3 Exception Handling
Program execution state No No
NMI Yes
IRRI0 = 1 Yes IEN0 = 1 Yes
No No
IRRI1 = 1 Yes IEN1 = 1 Yes
No No
IRREC2 = 1 Yes IENEC2 = 1 Yes
No No
IRRAD = 1 Yes IENAD = 1 Yes
No
I=0 Yes PC contents saved CCR contents saved I1
No
Branch to interrupt handling routine
[Legend] PC: Program counter CCR: Condition code register I bit of CCR I:
Figure 3.3 Flow up to Interrupt Acceptance
Rev. 3.00 May 15, 2007 Page 55 of 516 REJ09B0152-0300
3.6.1
REJ09B0152-0300
Internal processing Stack Vector fetch Internal processing Instruction prefetch of interrupt handling routine (1) (3) (5) (7) (9) (11)
Interrupt accepted Interrupt level determination Instruction Wait for end of instruction prefetch
Section 3 Exception Handling
Rev. 3.00 May 15, 2007 Page 56 of 516
Interrupt request signal
Internal address bus
Interrupt Exception Handling Sequence
Internal read signal
Internal write signal High
Internal data bus (2) (4) (6) (8)
(10)
(12)
(1): (9): (10): (11): (12):
Instruction prefetch address (Not executed. This is the contents of the saved PC and the return address.) Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((11) = (10)) First instruction of interrupt handling rou
(2)(4): Instruction code (Not executed.)
Figure 3.4 shows the interrupt exception handling sequence. The example shown is for the case where the program area and stack area are in a 16-bit and 2-state access space.
Figure 3.4 Interrupt Exception Handling Sequence
(3):
Instruction prefetch address (Not executed.)
(5):
SP-2
(7):
SP-4
(6)(8):
Saved PC and saved CCR
Section 3 Exception Handling
3.7
Stack Status after Exception Handling
Figures 3.5 shows the stack after completion of interrupt exception handling.
SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area Prior to start of interrupt exception handling
SP (R7) SP + 1 SP + 2 SP + 3 SP + 4
CCR CCR* PCH PCL Even address
PC and CCR saved to stack
After completion of interrupt exception handling
[Legend] PCH: Upper 8 bits of program counter (PC) PCL: Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word length, starting from an even-numbered address. * Ignored when returning from the interrupt handling routine.
Figure 3.5 Stack Status after Exception Handling 3.7.1 Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.4
Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Note: * Excluding EEPMOV instruction.
Interrupt Wait States
States 1 to 23 4 2 4 4 Total 15 to 37
Rev. 3.00 May 15, 2007 Page 57 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.8
3.8.1
Usage Notes
Notes on Stack Area Use
When word data is accessed in this LSI, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. To save register values, use PUSH.W Rn (MOV.W Rn, @-SP) or PUSH.L ERn (MOV.L ERn, @-SP). To restore register values, use POP.W Rn (MOV.W @SP+, Rn) or POP.L ERn (MOV.L @SP+, ERn). Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
PC H SP SP PC L
SP
R1L PC L
H'FEFC H'FEFD
H'FEFF
BSR instruction SP set to H'FEFF
MOV. B R1L, @-R7 Stack accessed beyond SP Contents of PC are lost H
[Legend] PC H: Upper byte of program counter PC L: Lower byte of program counter R1L: General register R1L Stack pointer SP:
Figure 3.6 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when an RTE instruction is executed, this also takes place in word size. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored.
Rev. 3.00 May 15, 2007 Page 58 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.8.2
Notes on Switching Functions of External Interrupt Pins
When PFCR and PMRB are rewritten to switch the functions of external interrupt pins and when the value of the ECPWME bit in AEGSR is rewritten to switch between selection and nonselection of IRQAEC, the following points should be observed. When a pin function is switched by rewriting PFCR or PMRB that controls an external interrupt pin (IRQAEC, IRQ1, or IRQ0), the interrupt request flag is set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching the pin function. When the value of the ECPWME bit in AEGSR that sets selection or non-selection of IRQAEC is rewritten, the interrupt request flag may be set to 1, even if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM output for the AEC). Therefore, be sure to clear the interrupt request flag to 0 after switching the pin function. Figure 3.7 shows the procedure for setting a bit in PFCR and PMRB and clearing the interrupt request flag. This procedure also applies to AEGSR setting. When switching a pin function, mask the interrupt before setting the bit in PFCR and PMRB (or AEGSR). After accessing PFCR and PMRB (or AEGSR), execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag to 0 is executed immediately after PFCR and PMRB (or AEGSR) access without executing an instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level. However, the procedure in figure 3.7 is recommended because IECPWM is an internal signal and determining its value is complicated.
Interrupts masked. (Another possibility is to disable the relevant interrupt in the interrupt enable register 1.)
I bit in CCR 1
Set PFCR and PMRB (or AEGSR) bit After setting PFCR and PMRB (or AEGSR) bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0
Execute NOP instruction
Clear interrupt request flag to 0
I bit in CCR 0
Interrupt mask cleared
Figure 3.7 PFCR and PMRB (or AEGSR) Setting and Interrupt Request Flag Clearing Procedure
Rev. 3.00 May 15, 2007 Page 59 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.8.3
Method for Clearing Interrupt Request Flags
Use the recommended method given below when clearing the flags in interrupt request registers (IRR1 and IRR2). * Recommended method Use a single instruction to clear flags. The bit manipulation instruction and byte-size data transfer instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 in IRR1) are given below. Example 1: BCLR #1, @IRR1:8 Example 2: MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101) * Example of a malfunction When flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1 (bit 1 in IRR1). MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time AND.B #B'11111101,R1L ..... Here, IRRI0 = 1 MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0 In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B instruction is executing. The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1, IRRI0 is also cleared. 3.8.4 Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. When an interrupt source flag is cleared to 0, the interrupt concerned will be ignored.
Rev. 3.00 May 15, 2007 Page 60 of 516 REJ09B0152-0300
Section 3 Exception Handling
3.8.5
Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. When an interrupt request is generated, an interrupt is requested to the CPU. At that time, if the CPU is executing an instruction that disables interrupts, the CPU always executes the next instruction after the instruction execution is completed. 3.8.6 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, even if an interrupt request other than the NMI is issued during transfer, the interrupt is not accepted until the transfer is completed. If the NMI interrupt request is issued, NMI exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an NMI interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
3.8.7
IENR Clearing
When an interrupt request is disabled by clearing the interrupt enable register or when the interrupt flag register is cleared, the interrupt request should be masked (I bit = 1). If the above operation is executed while the I bit is 0 and conflict between the instruction execution and the interrupt request generation occurs, exception handling, which corresponds to the interrupt request generated after instruction execution of the above operation is completed, is executed.
Rev. 3.00 May 15, 2007 Page 61 of 516 REJ09B0152-0300
Section 3 Exception Handling
Rev. 3.00 May 15, 2007 Page 62 of 516 REJ09B0152-0300
Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
The clock pulse generator is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, system clock divider, and on-chip oscillator. The subclock pulse generator consists of a subclock oscillator, on-chip oscillator clock divider, and subclock divider. Figure 4.1 shows a block diagram of the clock pulse generators.
E7_2 OSC1 OSC2
System clock oscillator
OSC
(fOSC) Rosc
OSC
(fOSC)
System clock divider
OSC OSC/8 OSC/16 OSC/32 OSC/64
Prescaler S (13 bits)
Rosc
On-chip oscillator (fROSC) System clock pulse generator On-chip oscillator Rosc/32 clock divider W/2 Subclock W/4 divider W/8
/2 to /8192
W W
(fW)
X1 X2
Subclock oscillator
W
(fW)
SUB W/2 W/4
OSCCR
Subclock pulse generator [Legend] OSCCR: Oscillator control register
Prescaler W (8 bits)
W/8 to W/1024
Figure 4.1 Block Diagram of Clock Pulse Generators The reference clock signals that drive the CPU and on-chip peripheral modules are and SUB. The system clock is divided by prescaler S to become a clock signal from /8192 to /2. W/4, which is 1/4th of the watch clock W, is divided by prescaler W to become a clock signal from W/1024 to W/8. Both the system clock and subclock signals are provided to the on-chip peripheral modules.
CPG0200A_000020020200
Rev. 3.00 May 15, 2007 Page 63 of 516 REJ09B0152-0300
Section 4 Clock Pulse Generators
4.1
Register Description
* Oscillator control register (OSCCR) 4.1.1 Oscillator Control Register (OSCCR)
OSCCR controls the subclock oscillator, on-chip feedback resistance, and on-chip oscillator.
Bit 7 Bit Name SUBSTP Initial Value 0 R/W R/W Description Subclock Oscillator Control Controls start and stop of the subclock oscillator. When the subclock is not used, set this bit to 1. 0: Subclock oscillator operates 1: Subclock oscillator stops 6 RFCUT 0 R/W On-chip Feedback Resistance Control Selects whether the on-chip feedback resistance in the system clock oscillator is used when an external clock is input or when the on-chip oscillator is used. After setting this bit in the state in which an external clock is input or the on-chip oscillator is used, temporarily transit to standby mode, watch mode, or subactive mode. The setting of whether the feedback resistance in the system clock oscillator is used or not takes effect when standby mode, watch mode, or subactive mode is entered. 0: On-chip feedback resistance in system clock oscillator is used 1: On-chip feedback resistance in system clock oscillator is not used 5 SUBSEL 0 R/W Subclock Select Selects by which oscillator the subclock pulse generator operates. 0: Subclock oscillator operates 1: On-chip oscillator operates Note: The SUBSEL bit setting can be changed only when the subclock is not being used.
Rev. 3.00 May 15, 2007 Page 64 of 516 REJ09B0152-0300
Section 4 Clock Pulse Generators
Bit 4, 3
Bit Name
Initial Value All 0
R/W
Description Reserved These bits are always read as 0 and cannot be modified.
2 1
OSCF
0 *
R
Reserved The write value should always be 0. OSC Flag Indicates by which oscillator the system clock pulse generator operates. 0: System clock oscillator operates 1: On-chip oscillator operates (system clock oscillator is halted)
0 Note: *
0
Reserved The write value should always be 0.
The value depends on the state of the E7_2 pin. Refer to table 4.1.
Rev. 3.00 May 15, 2007 Page 65 of 518 REJ09B0152-0300
Section 4 Clock Pulse Generators
4.2
System Clock Oscillator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Either the system clock oscillator or on-chip oscillator can be selected, as shown in figure 4.1. For the selecting method, see section 4.2.4, On-Chip Oscillator Selection Method. 4.2.1 Connecting Crystal Resonator
Figure 4.2 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance crystal resonator should be used. For notes on connecting, refer to section 4.5.2, Notes on Board Design.
C1 OSC1 C2
OSC2
Frequency
Manufacturer
Product Type NR-18
C1, C2 Recommendation Value 12 pF 20%
4.194304 MHz NIHON DEMPA KOGYO CO.,LTD.
Figure 4.2 Typical Connection to Crystal Resonator 4.2.2 Connecting Ceramic Resonator
Figure 4.3 shows a typical method of connecting a ceramic resonator. For notes on connecting, refer to section 4.5.2, Notes on Board Design.
C1 OSC1 C2 OSC2
Frequency 4.19 MHz Manufacturer C1, C2 Recommendation Value Murata Manufacturing Co., Ltd. 15 pF (on-chip) 47 pF (on-chip)
Figure 4.3 Typical Connection to Ceramic Resonator
Rev. 3.00 May 15, 2007 Page 66 of 516 REJ09B0152-0300
Section 4 Clock Pulse Generators
4.2.3
External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.4 shows a typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
External clock input
OSC2
Open
Figure 4.4 Example of External Clock Input 4.2.4 On-Chip Oscillator Selection Method
The on-chip oscillator is selected by the E7_2 pin input level during a reset. The methods for selecting the system clock oscillator and on-chip oscillator are shown in table 4.1. The input level on the E7_2 pin during a reset is pulled up or down using a resistor according to the selected oscillator, and fixed on exit from the reset state. When the on-chip oscillator is selected, a resonator no longer needs to be connected to the OSC1 and OSC2 pins. In such a case, fix the OSC1 pin to GND or leave it open, and leave the OSC2 pin open. Notes: 1. When programming or erasing the flash memory, such as performing on-board programming, the system clock oscillator must be selected. When the on-chip emulator is used, even though the on-chip oscillator is selected, connect a resonator or input an external clock. 2. When the on-chip debugger is connected, the value of the resistor should be high. When not connected, it is specified according to the selected oscillator. Table 4.1 Methods for Selecting System Clock Oscillator and On-Chip Oscillator
OSCF 1 0
Oscillator in System Clock Pulse E7_2 Pin Input Level (during Reset) Generator 0 1 On-chip oscillator System clock oscillator
Rev. 3.00 May 15, 2007 Page 67 of 518 REJ09B0152-0300
Section 4 Clock Pulse Generators
4.3
Subclock Oscillator
A subclock can be provided by connecting a crystal resonator or inputting an external clock. Either the subclock oscillator or on-chip oscillator can be selected, as shown in figure 4.1. For the selecting method, see section 4.3.4, On-Chip Oscillator Selection Method. 4.3.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator
Figure 4.5 shows an example of connecting a 32.768-kHz or 38.4-kHz crystal resonator. Notes described in section 4.5.2, Notes on Board Design also apply to this connection.
C1 X1
X2 C2
Frequency 38.4 kHz
Manufacturer EPSON TOYOCOM CORPORATION
Products Name Equivalent Series Resistance C-4-TYPE C-001R 30 k (max.) 35 k (max.)
32.768 kHz EPSON TOYOCOM CORPORATION C 1 = C 2 = 7 pF (typ.)
Note: Consult with the crystal resonator manufacturer to determine the parameters.
Figure 4.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator 1. When the resonator other than ones listed above is used, perform matching evaluation with the crystal resonator manufacture and connect it under the optimum condition. Even when the resonator listed above or the equivalent is used, as the oscillation characteristics depend on the board specification, perform matching evaluation on the mounting board. 2. Perform matching evaluation in the reset state (the RES pin is low) and on exit from the reset state (the RES pin is driven from low to high).
Rev. 3.00 May 15, 2007 Page 68 of 516 REJ09B0152-0300
Section 4 Clock Pulse Generators
Figure 4.6 shows the equivalent circuit of the crystal resonator.
CS LS X1 RS X2
CO
CO = 1.5 pF (typ.) RS = 14 k (typ.) fW = 32.768 kHz/38.4 kHz
Figure 4.6 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator 4.3.2 Pin Connection when not Using Subclock
When the subclock is not used, connect the X1 pin to GND and leave the X2 pin open, as shown in figure 4.7.
X1 GND X2 Open
Figure 4.7 Pin Connection when not Using Subclock
Rev. 3.00 May 15, 2007 Page 69 of 518 REJ09B0152-0300
Section 4 Clock Pulse Generators
4.3.3
External Clock Input Method
Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4.8.
X1
External clock input
X2
Open
Figure 4.8 Pin Connection when Inputting External Clock
Frequency Duty Watch Clock (W) 45% to 55%
4.3.4
On-Chip Oscillator Selection Method
The on-chip oscillator is selected by the SUBSEL bit in OSCCR. When the on-chip oscillator is selected, a resonator no longer needs to be connected to the X1 and X2 pins. In such a case, fix the X1 pin at GND.
Rev. 3.00 May 15, 2007 Page 70 of 516 REJ09B0152-0300
Section 4 Clock Pulse Generators
4.4
Prescalers
This LSI is equipped with two on-chip prescalers (prescaler S and prescaler W), which have different input clocks. Prescaler S is a 13-bit counter using the system clock () as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is an 8-bit counter using W/4, which is 1/4th of the watch clock W, as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. 4.4.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock () as its input clock. A divided output is used as an internal clock of an on-chip peripheral module. Prescaler S is initialized to H'0000 at a reset, and starts counting up on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, prescaler S stops and is initialized to H'0000. The CPU cannot read from or write to prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. In active (mediumspeed) mode and sleep (medium-speed) mode, the clock input to prescaler S is determined by the division ratio designated by the MA1 and MA0 bits in SYSCR1. 4.4.2 Prescaler W
Prescaler W is an 8-bit counter using W/4, which is 1/4th of the watch clock W, as its input clock. A divided output is used as an internal clock of an on-chip peripheral module. Prescaler W is initialized to H'00 at a reset, and starts counting up on exit from the reset state. In standby mode, prescaler W is halted. Even when transiting to watch mode, subactive mode, and subsleep mode, prescaler W continues operation.
Rev. 3.00 May 15, 2007 Page 71 of 518 REJ09B0152-0300
Section 4 Clock Pulse Generators
4.5
4.5.1
Usage Notes
Note on Resonators and Resonator Circuits
Resonator characteristics are closely related to board design. Therefore, resonators should be assigned after being carefully evaluated by the user in the masked ROM version and flash memory version, with referring to the examples shown in this section. Resonator circuit constants will differ depending on a resonator, stray capacitance in its mounting circuit, and other factors. Suitable constants should be determined in consultation with the resonator manufacturer. Design the circuit so that the oscillator pin is never applied voltages exceeding its maximum rating.
Vcc OSC1 Vss OSC2 RES X2 X1 AVcc
(Vss)
Figure 4.9 Example of Crystal and Ceramic Resonator Assignment
Rev. 3.00 May 15, 2007 Page 72 of 516 REJ09B0152-0300
Section 4 Clock Pulse Generators
Figure 4.10 (1) shows an example measuring circuit with the negative resistance recommended by the resonator manufacturer. Note that if the negative resistance of the circuit is less than that recommended by the resonator manufacturer, it may be difficult to start the main oscillator. If it is determined that oscillation does not occur because the negative resistance is lower than the level recommended by the resonator manufacturer, the circuit must be modified as shown in figure 4.10 (2) through (4). Which of the modification suggestions to use and the capacitor capacitance should be decided based upon evaluation results such as the negative resistance and the frequency deviation.
Modification point OSC1 C1 C1 OSC1
OSC2 C2 Negative resistance, addition of -R (1) Negative Resistance Measuring Circuit C2
OSC2
(2) Oscillator Circuit Modification Suggestion 1 Modification point
Modification point OSC1 C1 C1
C3 OSC1
C2
OSC2 C2
OSC2
(3) Oscillator Circuit Modification Suggestion 2
(4) Oscillator Circuit Modification Suggestion 3
Figure 4.10 Negative Resistance Measurement and Circuit Modification Suggestions
Rev. 3.00 May 15, 2007 Page 73 of 518 REJ09B0152-0300
Section 4 Clock Pulse Generators
4.5.2
Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the resonator circuit to prevent induction from interfering with correct oscillation (see figure 4.11).
Avoid Signal A Signal B C1 OSC1 C2 OSC2
Figure 4.11 Example of Incorrect Board Design Note: When a crystal resonator or ceramic resonator is connected, consult with the crystal resonator and ceramic resonator manufacturers to determine the circuit constants because the constants differ according to the resonator, stray capacitance of the mounting circuit, and so on. 4.5.3 Definition of Oscillation Stabilization Wait Time
Figure 4.12 shows the oscillation waveform (OSC2), system clock (), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an resonator connected to the system clock oscillator. As shown in figure 4.12, when a transition is made to active (high-speed/medium-speed) mode, from standby mode, watch mode, or subactive mode, in which the system clock oscillator is halted, the sum of the following two times (oscillation start time and wait time) is required. (1) Oscillation Start Time
The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the system clock starts to be generated.
Rev. 3.00 May 15, 2007 Page 74 of 516 REJ09B0152-0300
Section 4 Clock Pulse Generators
(2)
Wait Time
After the system clock is generated, the time required for the amplitude of the oscillation waveform to increase, the oscillation frequency to stabilize, and the CPU and peripheral functions to begin operating.
Oscillation waveform (OSC2)
System clock () Oscillation start time
Wait time
Operating mode
Standby mode, watch mode, or subactive mode
Oscillation stabilization wait time
Active (high-speed) mode or active (medium-speed) mode
Interrupt accepted
Figure 4.12 Oscillation Stabilization Wait Time As the oscillation stabilization wait time required is the same as the oscillation stabilization time (trc) at power-on, specified in the AC characteristics, set the STS2 to STS0 bits in SYSCR1 to specify the time longer than the oscillation stabilization time (trc). Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an resonator connected to the system clock oscillator, careful evaluation must be carried out on the mounting circuit before deciding the oscillation stabilization wait time. For the wait time, secure the time required for the amplitude of the oscillation waveform to increase and the oscillation frequency to stabilize. In addition, since the oscillation start time differs according to mounting circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the resonator manufacturer.
Rev. 3.00 May 15, 2007 Page 75 of 518 REJ09B0152-0300
Section 4 Clock Pulse Generators
4.5.4
Note on Subclock Stop State
To stop the subclock, a state transition should not be made except to mode in which the system clock operates. If the state transition is made to other mode, it may result in incorrect operation. 4.5.5 Note on the Oscillation Stabilization of Resonators
When a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. Depending on the individual resonator characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted, leading to an unstable system clock and incorrect operation of the microcomputer. If incorrect operation occurs, change the setting of the standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in the system control register 1 (SYSCR1)) to give a longer wait time. For example, if incorrect operation occurs with a wait time setting of 512 states, check the operation with a wait time setting of 1,024 states or more. If the same kind of incorrect operation occurs after a reset as after a state transition, hold the RES pin low for a longer period. 4.5.6 Note on Using Power-On Reset
The power-on reset circuit in this LSI adjusts the reset clear time by the capacitor capacitance, which is externally connected to the RES pin. The external capacitor capacitance should be adjusted to secure the oscillation stabilization time before reset clearing. For details, refer to section 19, Power-On Reset Circuit. 4.5.7 Note on Using On-Chip Emulator
When the on-chip emulator is used, system clock accuracy is necessary for flash memory programming/erasing. The frequency of the on-chip oscillator differs depending on the voltage and temperature conditions. Therefore, when using the on-chip emulator, the resonator must be connected to the OSC1 and OSC2 pins or an external clock must be supplied. In this case, the onchip oscillator is used for user program execution, and the system clock is used for flash memory programming/erasing. This control is handled when the E7_2 pin is fixed to high level during a reset by the on-chip emulator.
Rev. 3.00 May 15, 2007 Page 76 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
Section 5 Power-Down Modes
This LSI has eight modes of operation after a reset. These include a normal active (high-speed) mode and seven power-down modes, in which power consumption is significantly reduced. The module standby function reduces power consumption by selectively halting on-chip module functions. * Active (medium-speed) mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from OSC/8, OSC/16, OSC/32, and OSC/64. * Subactive mode The CPU and all on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from W, W/2, W/4, and W/8. * Sleep (high-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. * Sleep (medium-speed) mode The CPU halts. On-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from OSC/8, OSC/16, OSC/32, and OSC/64. * Subsleep mode The CPU halts. The on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from W, W/2, W/4, and W/8. * Watch mode The CPU halts. The on-chip peripheral modules are operable on the subclock. * Standby mode The CPU and all on-chip peripheral modules halt. * Module standby function Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units. Note: In this manual, active (high-speed) mode and active (medium-speed) mode are collectively called active mode.
Rev. 3.00 May 15, 2007 Page 77 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.1
Register Descriptions
The registers related to power-down modes are as follows. * System control register 1 (SYSCR1) * System control register 2 (SYSCR2) * Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2) 5.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby Selects the mode to transit after the execution of the SLEEP instruction. 0: A transition is made to sleep mode or subsleep mode. 1: A transition is made to standby mode or watch mode. For details, see table 5.2. 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W Standby Timer Select 2 to 0 Designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, or watch mode to active mode or sleep mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time. The relationship between the specified value and the number of wait states is shown in table 5.1. When an external clock is to be used, the minimum value (STS2 = 1, STS1 = 1, and STS0 = 1) is recommended. When the on-chip oscillator is to be used, the minimum value (STS2 = 1, STS1 = 1, and STS0 = 1) is recommended. If a setting other than the recommended value is made, operation may start before the end of the waiting time.
Rev. 3.00 May 15, 2007 Page 78 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
Bit 3
Bit Name LSON
Initial Value 0
R/W R/W
Description Selects the system clock () or subclock (SUB) as the CPU operating clock when watch mode is cleared. 0: The CPU operates on the system clock () 1: The CPU operates on the subclock (SUB)
2
TMA3
0
R/W
Selects the mode to which the transition is made after the SLEEP instruction is executed with bits SSBY and LSON in SYSCR1 and bits DTON and MSON in SYSCR2. For details, see table 5.2. Active Mode Clock Select 1 and 0 Select the operating clock frequency in active (mediumspeed) mode and sleep (medium-speed) mode. The MA1 and MA0 bits should be written to in active (highspeed) mode or subactive mode. 00: OSC/8 01: OSC/16 10: OSC/32 11: OSC/64
1 0
MA1 MA0
1 1
R/W R/W
Table 5.1
Bit STS2 0 STS1 0
Operating Frequency and Waiting Time
Operating Frequency and Waiting Time STS0 0 1 Waiting States 8,192 states 16,384 states 1,024 states 2,048 states 4,096 states 256 states 512 states 16 states 10 MHz 819.2 1,638.4 102.4 204.8 409.6 25.6 51.2 1.6 8 MHz 1,024.0* 2,048.0 128.0 256.0 512.0 32.0 64.0*2 2.0
1
6 MHz 1,365.3* 2,730.7 170.7 341.3 682.7* 42.7*
2 1 1
5 MHz 1,638.4 3,276.8 204.8 409.6 819.2* 51.2*
2 1
4.194MHz 3 MHz 1953.3 3906.5 244.2 488.3 976.6 61.0 122.1 3.8 2,730.7
2 MHz 4,096.0
5,461.3*1 8,192.0*1 341.3 682.7 1,365.3 85.3*
2
1
0 1
512.0 1,024.0 2,048.0 128.0*2 256.0 8.0
1
0
0 1
1
0 1
85.3*2 2.7
102.4 3.2
170.7 5.3
Notes: Time unit is s. : Recommended value when crystal resonator is used (Vcc = 2.7 V to 3.6 V) : Recommended value when ceramic resonator is used (Vcc = 2.2 V to 3.6 V) 1. Reference value when crystal resonator is used 2. Reference value when ceramic resonator is used
Rev. 3.00 May 15, 2007 Page 79 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit 7 to 5 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 4 NESEL 1 R/W Noise Elimination Sampling Frequency Select The subclock pulse generator generates the watch clock signal (W) and the system clock pulse generator generates the oscillator clock (OSC). This bit selects the sampling frequency of OSC when W is sampled. When a system clock is used, clear this bit to 0.When the onchip oscillator is selected, set this bit to 1. 0: Sampling rate is OSC/16. 1: Sampling rate is OSC/4. 3 DTON 0 R/W Direct Transfer on Flag Selects the mode to which the transition is made after the SLEEP instruction is executed with bits SSBY, TMA3, and LSON in SYSCR1 and bit MSON in SYSCR2. For details, see table 5.2. 2 MSON 0 R/W Medium Speed on Flag After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. 0: Operation in active (high-speed) mode 1: Operation in active (medium-speed) mode 1 0 SA1 SA0 0 0 R/W R/W Subactive Mode Clock Select 1 and 0 Select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 00: W/8 01: W/4 10: W/2 11: W
Rev. 3.00 May 15, 2007 Page 80 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.1.3
Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2)
CKSTPR1 and CKSTPR2 allow the on-chip peripheral modules to enter the standby state in module units. * CKSTPR1
Bit 7 6 5 4 Bit Name S3CKSTP ADCKSTP Initial Value 0 0 0 0 R/W R/W R/W Description Reserved This bit is always read as 0 and cannot be modified. SCI3 Module Standby*1 SCI3 enters standby mode when this bit is cleared to 0. Reserved This bit is always read as 0 and cannot be modified. A/D Converter Module Standby A/D converter enters standby mode when this bit is cleared to 0. 3 2 TB1CKSTP 0 0 R/W Reserved This bit is always read as 0 and cannot be modified. Timer B1 Module Standby Timer B1 enters standby mode when this bit is cleared to 0. 1
FROMCKSTP*
2
1
R/W
Flash Memory Module Standby Flash memory enters standby mode when this bit is cleared to 0.
0
RTCCKSTP
1
R/W
RTC Module Standby RTC enters standby mode when this bit is cleared to 0.
Rev. 3.00 May 15, 2007 Page 81 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
* CKSTPR2
Bit 7 6 Bit Name TWCKSTP Initial Value 0 0 R/W R/W Description Reserved This bit is always read as 0 and cannot be modified. Timer W Module Standby Timer W enters standby mode when this bit is cleared to 0. 5 IICCKSTP 0 R/W IIC2 Module Standby The IIC2 enters standby mode when this bit is cleared to 0. 4
SSUCKSTP
0
R/W
SSU Module Standby The SSU enters standby mode when this bit is cleared to 0.
3
AECCKSTP
0
R/W
Asynchronous Event Counter Module Standby The asynchronous event counter enters standby mode when this bit is cleared to 0.
2
WDCKSTP
1
R/W*3
Watchdog Timer Module Standby The watchdog timer enters standby mode when this bit is cleared to 0.
1
COMPCKSTP
0
R/W
Comparator Module Standby The comparators enter standby mode when this bit is cleared to 0.
0
0
Reserved This bit is always read as 0 and cannot be modified.
Notes: 1. When the SCI3 module standby is set, all registers in the SCI3 enter the reset state. 2. When using the on-chip emulator, set this bit to 1. 3. This bit is valid when the WDON bit in TCSRW is 0. If this bit is cleared to 0 while the WDON bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0. However, the watchdog timer does not enter module standby mode and continues operating. When the WDON bit is cleared to 0 by software, this bit is valid and the watchdog timer enters module standby mode.
Rev. 3.00 May 15, 2007 Page 82 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.2
Mode Transitions and States of LSI
Figure 5.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. The operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. RES input enables transitions from a mode to the reset state. Table 5.2 shows the transition conditions of each mode after the SLEEP instruction is executed and a mode to return by an interrupt. Table 5.3 shows the internal states of the LSI in each mode.
Rev. 3.00 May 15, 2007 Page 83 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
Reset state Program halt state Standby mode SLEEP d instruction 4 d SLEEP instruction
Program execution state Active (high-speed mode) g f SLEEP SLEEP instruction instruction
SLEEP instruction a 3 a EP ion Et SL truc s in
Pn EE tio SL truc s in
Program halt state Sleep (high-speed) mode
4
b
e SLEEP instruction 1
S ins LE tru EP cti on
Active (medium-speed) mode e j SLEEP instruction SLEEP instruction i2
SLEEP b instruction 3
Sleep (medium-speed) mode
1
Watch mode
e SLEEP instruction 1
h SLEEP instruction
i1 SLEEP instruction
Subactive mode
SLEEP c instruction 2
Subsleep mode
: Transition is made after exception handling is executed. Mode Transition Conditions (1) LSON a b c d e f g h i1 i2 j 0 0 1 0 x 0 0 0 1 1 0 MSON SSBY TMA3 DTON 0 1 x x x 0 1 1 x 1 0 0 0 0 1 1 0 0 1 1 1 1 x x 1 0 1 x x 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 2 3 4
Power-down modes Mode Transition Conditions (2) Interrupt Sources NMI, IRQ0, IRQ1, IRQAEC, COMP, RTC, WDT, AEC, and timer B1 All interrupts except IIC2 All interrupts NMI, IRQ0, IRQ1, IRQAEC, COMP, WDT, and AEC
x: Don't care
Note: A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupt handling is accepted.
Figure 5.1 Mode Transition Diagram
Rev. 3.00 May 15, 2007 Page 84 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
Table 5.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling
LSON MSON SSBY 0 1 0 1 0 1 x 0 1 x 0 1 0 1 0 1 1 0 1 1 x 0 1 x 0 1 x 0 0 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 TMA3 x x 0 0 1 1 1 x x 1 x x 0 0 1 1 1 x x 1 1 1 1 1 1 1 1 DTON 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 Transition Mode after SLEEP Instruction Execution Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Standby mode Watch mode Watch mode Watch mode Active (high-speed) mode (direct transition) Active (medium-speed) mode (direct transition) Subactive mode (direct transition) Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Standby mode Watch mode Watch mode Watch mode Active (high-speed) mode (direct transition) Active (medium-speed) mode (direct transition) Subactive mode (direct transition) Subsleep mode Watch mode Watch mode Watch mode Active (high-speed) mode (direct transition) Active (medium-speed) mode (direct transition) Subactive mode (direct transition) Transition Mode due to Interrupt Active (high-speed) mode Active (medium-speed) mode Active (high-speed) mode Active (medium-speed) mode Active (high-speed) mode Active (medium-speed) mode Subactive mode Active (high-speed) mode Active (medium-speed) mode Active (high-speed) mode Active (medium-speed) mode Active (high-speed) mode Active (medium-speed) mode Subactive mode Subactive mode Active (high-speed) mode Active (medium-speed) mode Subactive mode
Active (highspeed) mode
0 0 0 0 0 0 1 0 0 1
Active (mediumspeed) mode
0 0 0 0 0 0 1 0 0 1
Subactive mode
1 0 0 1 0 0 1
[Legend]
x: Don't care.
Rev. 3.00 May 15, 2007 Page 85 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
Table 5.3
Internal State in Each Operating Mode
Active Mode HighMediumspeed Functions Sleep Mode Highspeed Functions Mediumspeed Functions Watch Mode Halted Subactive Subsleep Mode Halted Functions Mode Halted Functions Standby Mode Halted Functions/ Halted Halted Retained Functions Halted Retained Halted Retained
Function System clock oscillator Subclock oscillator
speed Functions
Functions/ Functions/ Functions/ Halted Halted Functions Halted Halted Retained
Functions/ Functions Halted Halted Retained
CPU
Instructions RAM Registers I/O
Functions
Retained*1 Functions Functions Functions Functions Functions Functions Functions Functions
External interrupts
NMI IRQ0 IRQ1 IRQAEC
Peripheral Timer B1 modules Timer W
Functions
Functions
Functions
Functions
Functions/ Retained*2 Retained
Functions/
Functions/ Retained
Retained*2 Retained*2 Functions/ Functions/ Retained
Retained*3 Retained*3 WDT Functions/ Retained*5 RTC Functions/ Retained*6 Asynchronous event counter SCI3/ IrDA IIC2 SSU Retained Retained Reset Functions/ Functions/ Reset Functions Functions/ Functions/ Functions/
Retained*5 Retained*5 Retained*4 Functions/ Functions/ Retained
Retained*6 Retained*6 Functions Functions Functions
Retained*7 Retained*7 Retained Functions/ Retained Retained
Functions/ Retained
Retained*8 Retained*8 A/D Retained Functions/ Functions/ Retained
Retained*9 Retained*9 Comparator Functions Functions Functions Functions
Notes: 1. Register contents are retained. Output is the high-impedance state. 2. Functions if W/256 or W/1024 is selected as an internal clock. Halted and retained otherwise.
Rev. 3.00 May 15, 2007 Page 86 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
3. Functions if W, W/4, or W/16 is selected as an internal clock. Halted and retained otherwise. 4. Functions if the on-chip oscillator is selected. Halted and retained otherwise. 5. Functions if the on-chip oscillator is selected or if W/16 or W/256 is selected as an internal clock. Halted and retained otherwise. 6. Functions if the 32.768-kHz RTC is selected as an internal clock. Halted and retained otherwise. 7. Functions if W is selected as an internal clock. Halted and retained otherwise. 8. Functions if SUB/2 is selected as an internal clock. Halted and retained otherwise. 9. Functions if W/2 is selected as an internal clock. Halted and retained otherwise.
5.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the system clock oscillator, subclock oscillator, and on-chip peripheral modules function. In sleep (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed) mode to active (medium-speed) mode. When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an interrupt request signal is synchronous with the system clock, the maximum time of 2/ (s) may be delayed from the point at which an interrupt request signal occurs until the interrupt exception handling is started.
Rev. 3.00 May 15, 2007 Page 87 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.2.2
Standby Mode
In standby mode, the system clock oscillator stops, and the CPU and on-chip peripheral modules stop functioning except for the WDT, asynchronous event counter, and comparators. However, as long as the rated voltage is supplied, the contents of CPU registers and some on-chip peripheral module registers are retained. On-chip RAM contents will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O ports go to the high-impedance state. Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2. Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable bit. When a reset source is generated in standby mode, the system clock oscillator starts. If a reset is generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high. 5.2.3 Watch Mode
In watch mode, the system clock oscillator and CPU operation stop, and on-chip peripheral modules stop functioning except for the WDT, RTC, timer B1, asynchronous event counter, and comparators. However, as long as the rated voltage is supplied, the contents of CPU registers, some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain their state before the transition. Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in watch mode, the system clock oscillator starts. If a reset is generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high.
Rev. 3.00 May 15, 2007 Page 88 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.2.4
Subsleep Mode
In subsleep mode, the CPU operation stops but on-chip peripheral modules function except for the IIC2. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in subsleep mode, the system clock oscillator starts. If a reset is generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high. 5.2.5 Subactive Mode
In subactive mode, the system clock oscillator stops but on-chip peripheral modules function except for the IIC2. As long as a required voltage is applied, the contents of some registers of the on-chip peripheral modules are retained. Subactive mode is cleared by the SLEEP instruction. When subactive mode is cleared, a transition to subsleep mode, active mode, or watch mode is made, depending on the combination of bits SSBY, LSON, and TMA3 in SYSCR1 and bits MSON and DTON in SYSCR2. When a reset source is generated in subactive mode, the system clock oscillator starts. If a reset is generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high. The operating frequency of subactive mode is selected from W (watch clock), W/2, W/4, and W/8 by the SA1 and SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to the frequency which is set before the execution.
Rev. 3.00 May 15, 2007 Page 89 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.2.6
Active (Medium-Speed) Mode
In active (medium-speed) mode, the clock set by the MA1 and MA0 bits in SYSCR1 is used as the system clock, and the CPU and on-chip peripheral modules function. Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed) mode is cleared, a transition to standby mode is made depending on the combination of bits SSBY, LSON, and TMA3 in SYSCR1, a transition to watch mode is made depending on the combination of bits SSBY and TMA3 in SYSCR1, or a transition to sleep mode is made depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition to active (high-speed) mode or subactive mode is made by a direct transition. When the RES pin goes low, the CPU goes into the reset state and active (medium-sleep) mode is cleared.
Rev. 3.00 May 15, 2007 Page 90 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.3
Direct Transition
The CPU can execute programs in two modes: active and subactive modes. A direct transition is made between these two modes without stopping program execution. A direct transition can also be made when the operating clock is changed in active and subactive modes. The transition is made via the sleep or watch mode, by setting the DTON bit in SYSCR2 to 1 to execute a SLEEP instruction. After the mode transition, direct transition interrupt exception handling starts. Note that if a direct transition is attempted while the I bit in CCR is 1, the transition is made to the sleep or watch mode, though not returning from the mode. 5.3.1 Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made to active (medium-speed) mode via sleep mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tcyc after transition)............(1) Example: When osc/8 is selected as the CPU operating clock after the transition
Direct transition time = (2 + 1) x 1tosc + 14 x 8tosc = 115tosc For the legend of symbols used above, refer to section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 91 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.3.2
Direct Transition from Active (High-Speed) Mode to Subactive Mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY, TMA3, and LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tsubcyc after transition)........(2) Example: When w/8 is selected as the subactive operating clock after the transition
Direct transition time = (2 + 1) x 1tosc + 14 x 8tw = 3tosc + 112tw For the legend of symbols used above, refer to section 21, Electrical Characteristics. 5.3.3 Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (3). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tcyc after transition)...........(3) Example: When osc/8 is selected as the CPU operating clock before the transition
Direct transition time = (2 + 1) x 8tosc + 14 x 1tosc = 38tosc For the legend of symbols used above, refer to section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 92 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.3.4
Direct Transition from Active (Medium-Speed) Mode to Subactive Mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY, LSON, and TMA3 bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (4). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tcyc before transition) + (Number of interrupt exception handling execution states) x (tsubcyc after transition)......(4) Example: When osc/8 and w/8 are selected as the CPU operating clock before and after the transition, respectively
Direct transition time = (2 + 1) x 8tosc + 14 x 8tw = 24tosc + 112tw For the legend of symbols used above, refer to section 21, Electrical Characteristics. 5.3.5 Direct Transition from Subactive Mode to Active (High-Speed) Mode
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to active (highspeed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (5). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + (Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states) x (tcyc after transition)...............................................(5) Example: When w/8 is selected as the CPU operating clock after the transition and wait time = 8192 states
Direct transition time = (2 + 1) x 8tw + (8192 + 14) x 1tosc = 24tw + 8206tosc For the legend of symbols used above, refer to section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 93 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.3.6
Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (6). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + (Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states) x (tcyc after transition)................................................(6) Example: When w/8 and osc/8 are selected as the CPU operating clock before and after the transition, respectively, and wait time = 8192 states
Direct transition time = (2 + 1) x 8tw + 8192 x 1tosc + 14 x 8tosc = 24tw + 8304tosc For the legend of symbols used above, refer to section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 94 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.3.7
Notes on External Input Signal Changes before/after Direct Transition
* Direct transition from active (high-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.6.2, Notes on External Input Signal Changes before/after Standby Mode. * Direct transition from active (medium-speed) mode to subactive mode Since the mode transition is performed via watch mode, see section 5.6.2, Notes on External Input Signal Changes before/after Standby Mode. * Direct transition from subactive mode to active (high-speed) mode Since the mode transition is performed via watch mode, see section 5.6.2, Notes on External Input Signal Changes before/after Standby Mode. * Direct transition from subactive mode to active (medium-speed) mode Since the mode transition is performed via watch mode, see section 5.6.2, Notes on External Input Signal Changes before/after Standby Mode.
Rev. 3.00 May 15, 2007 Page 95 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.4
Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the clock supply to modules stops to enter the power-down mode. Module standby mode enables each on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each module in CKSTPR1 and CKSTPR2 to 0 and cancels the mode by setting the bit to 1. (See section 5.1.3, Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2).)
5.5
On-Chip Oscillator and Operation Mode
The on-chip oscillator can be used as the clock source for the watchdog timer (WDT), subclock generation circuit (W = ROSC/32), and system clock generation circuit (OSC = ROSC). When the on-chip oscillator is used as the clock source for the watchdog timer (WDT), it operates in any modes, such as active, sleep, subactive, subsleep, watch, and standby modes. When the on-chip oscillator is used as the clock source for the subclock generation circuit, it stops in standby mode and operates in other modes. When the on-chip oscillator is used only as the clock source for the system clock generation circuit, it operates in active and sleep modes but halts the operation in subactive, subsleep, watch, and standby modes. When the on-chip oscillator is not used as the clock source for the watchdog timer (WDT), subclock generation circuit, or system clock generation circuit, it halts the operation. The on-chip oscillator operates at a reset and after a reset, because the watchdog timer (WDT) selects the on-chip oscillator as the clock source for the initial value.
Rev. 3.00 May 15, 2007 Page 96 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
5.6
5.6.1
Usage Notes
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while the SSBY and TMA3 bits in SYSCR1 and the LSON bit in SYSCR1 are cleared to 0, a transition is made to standby mode. At the same time, pins go to the high-impedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows the timing in this case.
Internal data bus
SLEEP instruction fetch
Next instruction fetch Internal processing High-impedance Standby mode
SLEEP instruction execution Pins Port output
Active (high-speed) mode or active (medium-speed) mode
Figure 5.2 Standby Mode Transition and Pin States 5.6.2 (1) Notes on External Input Signal Changes before/after Standby Mode When External Input Signal Changes before/after Standby Mode or Watch Mode
When an external input signal such as NMI, IRQ0, IRQ1, or IRQAEC is input, both the high- and low-level widths of the signal must be at least two cycles of system clock or subclock SUB (referred to together in this section as the internal clock). As the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. Ensure that external input signals conform to the conditions stated in (3), Recommended Timing of External Input Signals, below.
Rev. 3.00 May 15, 2007 Page 97 of 516 REJ09B0152-0300
Section 5 Power-Down Modes
(2)
When External Input Signals cannot be Captured because Internal Clock Stops
The case of falling edge capture is shown in figure 5.3. As shown in the case marked "Capture not possible," when an external input signal falls immediately after a transition to active mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc. (3) Recommended Timing of External Input Signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in "Capture possible: case 1." External input signal capture is also possible with the timing shown in "Capture possible: case 2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured.
Wait for oscillation stabilization
Operating mode
Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc tcyc tsubcyc
Standby mode or watch mode tcyc tsubcyc
Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc
or SUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signal
Figure 5.3 External Input Signal Capture when Signal Changes before/after Standby Mode or Watch Mode (4) Input Pins to which these Notes Apply
NMI, IRQ0, IRQ1, IRQAEC, and ADTRG
Rev. 3.00 May 15, 2007 Page 98 of 516 REJ09B0152-0300
Section 6 ROM
Section 6 ROM
The features of the 16-Kbyte flash memory built into the flash memory (F-ZTAT) version are summarized below. * Programming/erasing methods The flash memory is programmed 128 bytes at a time. Erasure is performed in single-block units. The flash memory is configured as follows: 1 Kbyte x 4 blocks and 12 Kbytes x 1 block. To erase the entire flash memory, each block must be erased in turn. * On-board programming On-board programming/erasure can be done in boot mode, in which the boot program built into this LSI is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasure. * Power-down mode Operation of the power supply circuit can be partly halted in subactive mode. As a result, flash memory can be read with low power consumption. * Module standby mode Use of module standby mode enables this module to be placed in standby mode independently when not used. (For details, refer to section 5.4, Module Standby Function.) However, when using the on-chip emulator debugger, set the FROMCKSTP bit in clock halt register 1 to 1. Note: The system clock oscillator must be used when programming or erasing the flash memory.
ROM3560A_000120030300
Rev. 3.00 May 15, 2007 Page 99 of 516 REJ09B0152-0300
Section 6 ROM
6.1
Block Configuration
Figure 6.1 shows the block configuration of flash memory. The thick lines indicate erasing a block, the narrow lines indicate programming units, and the values are addresses. The 16-Kbyte flash memory is divided into 1 Kbyte x 4 blocks and 12 Kbytes x 1 block. Erasure is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
H'0000 Erasing unit 1 Kbyte H'0380 H'0400 Erasing unit 1 Kbyte H'0780 H'0800 Erasing unit 1 Kbyte H'0B80 H'0C00 Erasing unit 1 Kbyte H'0F80 H'1000 Erasing unit 12 Kbytes H'1080 H'0C80 H'0880 H'0480 H'0080
H'0001 H'0081
H'0002 H'0082
Programming unit: 128 bytes
H'007F H'00FF
H'0381 H'0401 H'0481
H'0382 H'0402 H'0482 Programming unit: 128 bytes
H'03FF H'047F H'04FF
H'0781 H'0801 H'0881
H'0782 H'0802 H'0882 Programming unit: 128 bytes
H'07FF H'087F H'08FF
H'0B81 H'0C01 H'0C81
H'0B82 H'0C02 H'0C82 Programming unit: 128 bytes
H'0BFF H'0C7F H'0CFF
H'0F81 H'1001 H'1081
H'0F82 H'1002 H'1082 Programming unit: 128 bytes
H'0FFF H'107F H'10FF
H'3F80
H'3F81
H'3F82
H'3FFF
Figure 6.1 Flash Memory Block Configuration
Rev. 3.00 May 15, 2007 Page 100 of 516 REJ09B0152-0300
Section 6 ROM
6.2
Register Descriptions
The flash memory has the following registers. * * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) Flash Memory Control Register 1 (FLMCR1)
6.2.1
FLMCR1 is a register that makes the flash memory enter the programming mode, programmingverifying mode, erasing mode, or erasing-verifying mode. For details on register setting, refer to section 6.4, Flash Memory Programming/Erasure.
Bit 7 6 Bit Name SWE Initial Value 0 0 R/W R/W Description Reserved This bit is always read as 0. Software Write Enable When this bit is set to 1, flash memory programming/erasure is enabled. When this bit is cleared to 0, other FLMCR1 register bits and all EBR1 bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1, the flash memory enters to the erasure setup state. When it is cleared to 0, the erasure setup state is released. Set this bit to 1 before setting the E bit in FLMCR1 to 1. 4 PSU 0 R/W Program Setup When this bit is set to 1, the flash memory enters to the programming setup state. When it is cleared to 0, the programming setup state is released. Set this bit to 1 before setting the P bit in FLMCR1 to 1.
Rev. 3.00 May 15, 2007 Page 101 of 518 REJ09B0152-0300
Section 6 ROM
Bit 3
Bit Name EV
Initial Value 0
R/W R/W
Description Erase-Verify When this bit is set to 1, the flash memory enters to erasing-verifying mode. When it is cleared to 0, erasingverifying mode is released.
2
PV
0
R/W
Program-Verify When this bit is set to 1, the flash memory enters the programming-verifying mode. When it is cleared to 0, programming-verifying mode is released.
1
E
0
R/W
Erase When this bit is set to 1 while SWE=1 and ESU=1, the flash memory enters the erasing mode. When it is cleared to 0, the erasing mode is released.
0
P
0
R/W
Program When this bit is set to 1 while SWE=1 and PSU=1, the flash memory enters the programming mode. When it is cleared to 0, the programming mode is released.
6.2.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that indicates the state of flash memory programming/erasure. FLMCR2 is a read-only register, and should not be written to.
Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates that an error has occurred during programming or erasing flash memory. When this bit is set to 1, flash memory enters the error-protection state. See section 6.5.3, Error Protection, for details. 6 to 0 All 0 Reserved These bits are always read as 0.
Rev. 3.00 May 15, 2007 Page 102 of 516 REJ09B0152-0300
Section 6 ROM
6.2.3
Erase Block Register 1 (EBR1)
EBR1 specifies the erase block of flash memory. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0.
Bit 7 to 5 Bit Name Initial Value All 0 R/W Description Reserved Although these bits are readable/writable, only 0 should be written to. When this bit is set to 1, a12-Kbyte area of H'1000 to H'3FFF will be erased. When this bit is set to 1, a 1-Kbyte area of H'0C00 to H'0FFF will be erased. When this bit is set to 1, a 1-Kbyte area of H'0800 to H'0BFF will be erased. When this bit is set to 1, a 1-Kbyte area of H'0400 to H'07FF will be erased. When this bit is set to 1, a 1-Kbyte area of H'0000 to H'03FF will be erased.
4 3 2 1 0
EB4 EB3 EB2 EB1 EB0
0 0 0 0 0
R/W R/W R/W R/W R/W
6.2.4
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when this LSI enters the subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Bit 7 Bit Name PDWND Initial Value 0 R/W R/W Description Power-Down Disable When this bit is 0 and a transition is made to subactive mode, the flash memory enters the power-down mode. When this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. Reserved These bits are always read as 0.
6 to 0
All 0
Rev. 3.00 May 15, 2007 Page 103 of 518 REJ09B0152-0300
Section 6 ROM
6.2.5
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1, and FLPWCR.
Bit 7 Bit Name FLSHE Initial Value 0 R/W R/W Description Flash Memory Control Register Enable Flash memory control registers can be accessed when this bit is set to 1. Flash memory control registers cannot be accessed when this bit is set to 0. 6 to 0 All 0 Reserved These bits are always read as 0.
6.3
On-Board Programming Modes
The available mode for programming/erasing of the flash memory is boot mode, which enables on-board programming/erasure. On-board programming/erasure can also be performed in user program mode. When this LSI starts after releasing the reset state, it enters a mode depending on the signal levels on the TEST, NMI , and E7_0 pins, as shown in table 6.1. The input level of each pin must be stable four states before the reset ends. When entering the boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control program is executed. This can be used for initializing flash memory mounted on the user board or for a forcible recovery if flash memory cannot be programmed or erased in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user programming/erasing control program prepared by the user. Table 6.1
TEST 0 0 [Legend] x: Don't care.
Setting Programming Modes
NMI 1 0 E7_0 x 1 LSI State after Reset Released User Mode Boot Mode
Rev. 3.00 May 15, 2007 Page 104 of 516 REJ09B0152-0300
Section 6 ROM
6.3.1
Boot Mode
Table 6.2 shows the boot mode operations between a reset released and a branch to the programming control program. This LSI includes a system clock oscillator which is operated by a resonator or an external clock and on-chip oscillator. In Boot Mode, since the system clock oscillator is selected, connect a resonator to OSC1 and OSC2, or an external clock signal to OSC1. 1. When the boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 6.4, Flash Memory Programming/Erasure. 2. SCI3 is set to the asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. The inversion function of the TXD and RXD pins by SPCR is set to "Not to be inverted," so do not put inverters between the host and this LSI. 3. When the boot program is initiated, this LSI measures the low-level period of serial communication data (H'00) continuously transmitted in asynchronous mode from the host. This LSI then calculates the bit rate of the transfer from the host, and adjusts the SCI3 bit rate to match that of the host. The reset signal should be negated while the RXD pin is driven high. The RXD and TXD pins should be pulled up on the board if necessary. After the reset signal is negated, it takes approximately 100 states before this LSI is ready to measure the low-level period. 4. After matching the bit rates, SCI3 transmits one byte of H'00 to the host to indicate the completion of bit rate adjustment. The host should confirm that it has received this adjustment end code (H'00) normally and then transmit one byte of H'55 to this LSI. If reception could not be performed normally, initiate the boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and this LSI. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 6.3. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The programming control program transmitted from the host can be stored in the area from H'FB80 to H'FF7F. The boot program area cannot be used until control of the execution is switched from the boot program to the programming control program.
Rev. 3.00 May 15, 2007 Page 105 of 518 REJ09B0152-0300
Section 6 ROM
6. Before branching to the programming control program, this LSI terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR3 to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transferring program data or verify data to the host. The TXD pin is driven high (PCR32 = 1, P32 = 1). The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program because the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. The boot mode can be released by a reset. Hold the reset signal low at least 20 states and then set the NMI pin before negating the reset signal. The boot mode is also released when a WDT overflow occurs. 8. Do not change the TEST pin and NMI pin input levels in boot mode.
Rev. 3.00 May 15, 2007 Page 106 of 516 REJ09B0152-0300
Section 6 ROM
Table 6.2
Item
Boot Mode Operation
Host Operation Processing Contents Communication Contents LSI Operation Processing Contents Branches to boot program after releasing reset state. Boot program initiation
Boot mode initiation
Bit rate adjustment
Continuously transmits data H'00 at specified bit rate.
H'00, H'00 . . . H'00
Transmits data H'55 when data H'00 is received error-free.
H'00
* Measures low-level period of receive data H'00. * Calculates bit rate and sets BRR in SCI3. * Transmits data H'00 to host as adjustment end code. H'55 reception.
H'55
Flash memory erase
Boot program erase error
H'FF
H'AA reception
H'AA
Checks flash memory data, erases all flash memory blocks when data has been written to and then transmits data H'AA to host. (If erasure fails, transmits data of H'FF to host and aborts operation.)
Transfer of programming control program
Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (lower byte following upper byte)
Low-order byte and high-order byte Echoback
Echobacks the 2-byte data received to host.
Transmits 1-byte of programming control program (repeated for N times)
H'XX Echoback
Echobacks received data to host and also transfers it to RAM. (repeated for N times)
H'AA reception
H'AA
Transmits data H'AA to host.
Branches to programming control program transferred to on-chip RAM and starts execution.
Rev. 3.00 May 15, 2007 Page 107 of 518 REJ09B0152-0300
Section 6 ROM
Table 6.3
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible
System Clock Frequency Range of LSI 8 to 10 MHz 4 to 10 MHz 2 to 10 MHz
Host Bit Rate 9,600 bps 4,800 bps 2,400 bps
6.3.2
Programming/Erasure in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user programming/erasing control program. The user must prepare the settings for branching to the user programming/erasing control program and means to transfer programming data for on-board programming. The flash memory must contain the user programming/erasing control program or a program that transfer the user programming/erasing control program from external memory. Since the flash memory cannot be read during programming/erasure, transfer the user programming/erasing control program to on-chip RAM, as in boot mode. Figure 6.2 shows a sample procedure for programming/erasure in user program mode. Prepare a user programming/erasing control program in accordance with the description in section 6.4, Flash Memory Programming/Erasure. The system clock oscillator must be used when programming or erasing the flash memory.
Starting after releasing reset state No Programming or erasure? Yes Transfer user programming/erasing control program to RAM Branch to user programming/erasing control program in RAM Branch to flash memory application program
Execute user programming/erasing control program (flash memory programmed)
Branch to flash memory application program
Figure 6.2 Programming/Erasing Flowchart Example in User Program Mode
Rev. 3.00 May 15, 2007 Page 108 of 516 REJ09B0152-0300
Section 6 ROM
6.4
Flash Memory Programming/Erasure
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Programming mode, programming-verifying mode, erasing mode, and erasing-verifying mode. The programming control program in boot mode and the user programming/erasing control program in user program mode use these operating modes in combination to perform programming/erasure. Flash memory programming and erasing should be performed in accordance with the descriptions in section 6.4.1, Programming/ProgrammingVerifying and section 6.4.2, Erasing/Erasing-Verifying, respectively. 6.4.1 Programming/Programming-Verifying
When writing data or programs to the flash memory, the programming/programming-verifying flowchart shown in figure 6.3 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be performed on an erased area. Do not reprogram an address to which data has already been programmed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if programming fewer than 128 bytes. In this case, the remaining area must be filled with H'FF. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation according to table 6.4, and additional programming data computation according to table 6.5. 4. Consecutively transfer 128 bytes of data in bytes from the reprogramming data area or additional-programming data area to the flash memory. The programming address and 128byte data are latched in the flash memory. The lower eight bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Table 6.6 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verifying address, write 1-byte of data H'FF to an address whose lower two bits are B'00. Verifying data can be read in words or in longwords from the address to which a dummy write was performed.
Rev. 3.00 May 15, 2007 Page 109 of 518 REJ09B0152-0300
Section 6 ROM
8. The maximum number of repetitions of the programming/programming-verifying sequence of the same bit is 1,000.
Write pulse application subroutine Apply Write Pulse Enable WDT Set PSU bit to 1 Wait 50 s Set P bit to 1 Wait (Wait time = programming time) Clear P bit to 0 Wait 5 s Clear PSU bit to 0 Wait 5 s Disable WDT End Sub
Write 128-byte reprogramming data in RAM consecutively to flash memory
START Set SWE bit to 1 Wait 1 s *
Store 128-byte programming data in programming data area and reprogramming data area
n=1 m=0
Apply Write pulse Set PV bit to 1 Wait 4 s Set block start address as verifying address Dummy write H'FF to verifying address Wait 2 s Read verifying data Increment address Verifying data = write data? Yes n6? Yes No No m=1 *
nn+1
Additional-programming data computation Reprogramming data computation
No
128-byte of data verified? Yes Clear PV bit to 0 Wait 2 s n 6? Yes No
Write 128-byte additional-programming data in RAM to flash memory
Sub-Routine-Call Apply Write Pulse No n 1000 ? No Clear SWE bit to 0 Wait 100 s Programming failure Yes
m=0? Yes Clear SWE bit to 0 Wait 100 s End of programming
Note: * The RTS instruction must not be used during the following periods. 1. A period from programming 128-byte data to flash memory until clearing the P bit 2. A period from dummy-writing of H'FF to a verifying address until reading verifying data
Figure 6.3 Program/Program-Verify Flowchart
Rev. 3.00 May 15, 2007 Page 110 of 516 REJ09B0152-0300
Section 6 ROM
Table 6.4
Reprogramming Data Computation Table
Verifying Data 0 1 0 1 Reprogramming Data Comments 1 0 1 1 Programming completed Needs to be programmed Remains in erased state
Programming Data 0 0 1 1
Table 6.5
Additional-Program Data Computation Table
Verify Data 0 1 0 1 Additional-Program Data 0 1 1 1 Comments Needs to be programmed additionally No additional programming No additional programming No additional programming
Reprogram Data 0 0 1 1
Table 6.6
Programming Time
Programming Time 30 s 200 s Additional Programming Time 10 s Comments
n (Programming Count) 1 to 6 times 7 to 1,000 times
Note: Time shown in s.
Rev. 3.00 May 15, 2007 Page 111 of 518 REJ09B0152-0300
Section 6 ROM
6.4.2
Erasing/Erasing-Verifying
When erasing flash memory, the erasing/erasing-verifying flowchart shown in figure 6.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasure is performed in block units. Select a single block to be erased through erase block register 1 (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erasing time. 4. The watchdog timer (WDT) is set to prevent the flash memory overerasing due to program crush, etc. An overflow cycle of approximately 19.8 ms is adequate. 5. For writing dummy data to a verifying address, write one byte of data H'FF to an address whose lower two bits are B'00. Verifying data can be read in longwords from the address to which a dummy data is written. 6. If the read data is not erased successfully, set erasing mode again, and repeat the erasing/erasing-verifying sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 6.4.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts including the NMI interrupt are disabled while flash memory is being programmed or erased or while the boot program is executed for the following three reasons. 1. An interrupt during programming/erasure may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before programming the vector address or during programming/erasure, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
Rev. 3.00 May 15, 2007 Page 112 of 516 REJ09B0152-0300
Section 6 ROM
Erase start Set SWE bit to 1 Wait 1 s n=1 Set EBR1 Enable WDT Set ESU bit to 1 Wait 100 s Set E bit to 1 Wait 10 ms Clear E bit to 0 Wait 10 s Clear ESU bit to 0 Wait 10 s Disable WDT Set EV bit to 1 Wait 20 s
Set block start address to verifying address
Dummy write H'FF to verifying address Wait 2 s Read verifying data No Increment address Verifying data = all 1s ? Yes No Last address of block ? Yes Clear EV bit to 0 Wait 4 s No Clear EV bit to 0 Wait 4s Yes
*
nn+1
All erase block erased ? Yes Clear SWE bit to 0 Wait 100 s End of erasing
n 100 ? No Clear SWE bit to 0 Wait 100 s Erase failure
Note: *The RTS instruction must not be used during a period from dummy-writing of H'FF to a verifying address until reading verifying data
Figure 6.4 Erase/Erase-Verify Flowchart
Rev. 3.00 May 15, 2007 Page 113 of 518 REJ09B0152-0300
Section 6 ROM
6.5
Programming/Erasing Protection
There are three types of flash memory programming/erasing protection; hardware protection, software protection, and error protection. 6.5.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to the reset state, subactive mode, subsleep mode, watch mode, or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), and erase block register 1 (EBR1) are initialized. For a reset by the RES pin, the reset state is entered when the RES signal is held low until oscillation stabilizes after switching on. For a reset during operation, hold the RES signal low for the RES pulse width specified in the AC Characteristics section. 6.5.2 Software Protection
Software protection can protect programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is enabled, setting the P or E bit in FLMCR1 does not cause a transition to programming mode or erasing mode. By setting the erase block register 1 (EBR1), erasing protection can be set for individual blocks. When EBR1 is set to H'00, erasing protection is set for all blocks. 6.5.3 Error Protection
Error protection is a state in which programming/erasure is forcibly aborted when an error is detected because CPU crush occurs during flash memory programming/erasure, or operation is not performed in accordance with the programming/erasing algorithm. Aborting programming/erasure prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory address being programmed or erased is read (including vector read and instruction fetch) * Exception handling excluding a reset is started during programming/erasure * When the SLEEP instruction is executed during programming/erasure
Rev. 3.00 May 15, 2007 Page 114 of 516 REJ09B0152-0300
Section 6 ROM
The FLMCR1, FLMCR2, and EBR1 settings are retained, however programming mode or erasing mode is aborted when the error occurred. Programming mode or erasing mode cannot be reentered by re-setting the P or E bit. However, settings of the PV and EV bits are retained, and a transition can be made to the verifying mode. The error protection state can be cleared only by a reset.
6.6
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read at high speed. * Power-down operating mode The power supply circuit of flash memory can be partly halted. As a result, flash memory can be read with low power consumption. * Standby mode All flash memory circuits are halted. Table 6.7 shows the correspondence between the operating modes of this LSI and the flash memory. In subactive mode, the flash memory can be set to operate in power-down mode with the PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from the power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 s, even when the external clock is being used. Table 6.7 Flash Memory Operating States
Flash Memory Operating State LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Watch mode Standby mode PDWND = 0 (Initial Value) Normal operating mode Power-down mode Normal operating mode Standby mode Standby mode Standby mode PDWND = 1 Normal operating mode Normal operating mode Normal operating mode Standby mode Standby mode Standby mode
Rev. 3.00 May 15, 2007 Page 115 of 518 REJ09B0152-0300
Section 6 ROM
6.7
Notes on Setting Module Standby Mode
When the flash memory is set to enter the module standby mode, the system clock supply is stopped to the module, the function is stopped, and the state is the same as that in standby mode. Also programming is stopped in the flash memory. Therefore operation program should be transferred to the RAM and the program should run in the RAM. Then the flash memory should be set to enter the module standby mode. If an interrupt is generated in module standby mode, the vector address cannot be fetched. As a result, the program may run away. Before the flash memory is set to enter module standby mode, the corresponding bit in the interrupt enable register should be cleared to 0 and the I bit in CCR should be set to 1. Then after the flash memory enters the module standby mode, the NMI interrupt request should not be generated.
Transfer execution program to RAM (user area) Clear corresponding bit in interrupt enable register to 0
Set I bit in CCR to 1
Jump to address of execution program in RAM Clear FROMCKSTP bit in CRSTPR1 to 0
Figure 6.5 Module Standby Mode Setting
Rev. 3.00 May 15, 2007 Page 116 of 516 REJ09B0152-0300
Section 7 RAM
Section 7 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification Flash memory version Masked ROM version H8/38602RF H8/38602R H8/38600R RAM Size RAM Address 1 Kbyte 1 Kbyte 512 bytes H'FB80 to H'FF7F H'FB80 to H'FF7F H'FD80 to H'FF7F
RAM0500A_000120030300
Rev. 3.00 May 15, 2007 Page 117 of 516 REJ09B0152-0300
Section 7 RAM
Rev. 3.00 May 15, 2007 Page 118 of 516 REJ09B0152-0300
Section 8 I/O Ports
Section 8 I/O Ports
The H8/38602R Group has 13 general I/O ports and six general input-only ports. Port 8 is a large current port, which can drive 15 mA (@VOL = 1.0 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings. The registers for selecting these functions can be divided into two types: those included in I/O ports and those included in each on-chip peripheral module. General I/O ports are comprised of the port control register for controlling inputs/outputs and the port data register for storing output data and can select inputs/outputs in bit units. For details on the execution of bit manipulation instructions to the port data register (PDR), see section 2.8.3, Bit-Manipulation Instruction. For details on block diagrams for each port, see appendix B.1, I/O Port Block Diagrams.
8.1
Port 1
Port 1 is an I/O port also functioning as an asynchronous event counter input pin, timer W I/O pin, RTC output pin, CLKOUT output pin, and interrupt input pin. Figure 8.1 shows its pin configuration.
Port 1
P12/IRQAEC/AECPWM P11/AEVL/FTCI (/IRQ1) P10/AEVH/FTIOA/TMOW/CLKOUT
Figure 8.1 Port 1 Pin Configuration Port 1 has the following registers. * * * * Port data register 1 (PDR1) Port control register 1 (PCR1) Port pull-up control register 1 (PUCR1) Port mode register 1 (PMR1)
Rev. 3.00 May 15, 2007 Page 119 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.1.1
Port Data Register 1 (PDR1)
PDR1 is a register that stores data of port 1.
Bit 7 to 3 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 2 1 0 P12 P11 P10 0 0 0 R/W R/W R/W If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
8.1.2
Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit 7 to 3 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 2 1 0 PCR12 PCR11 PCR10 0 0 0 W W W Setting a PCR1 bit to 1 makes the corresponding pin (P12 to P10) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid when the corresponding pin is designated as a general I/O pin. PCR3 is a write-only register. The read value is undefined.
Rev. 3.00 May 15, 2007 Page 120 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.1.3
Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS of the port 1 pins in bit units.
Bit 7 to 3 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 2 1 0 PUCR12 PUCR11 PUCR10 0 0 0 R/W R/W R/W When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
8.1.4
Port Mode Register 1 (PMR1)
PMR1 controls the selection of functions for port 1 pins.
Bit 7, 6 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 5 IRQAEC 0 R/W P12/IRQAEC/AECPWM Pin Function Switch 0: P12 I/O pin 1: IRQAEC input pin or AECPWM output pin 4 3 FTCI* AEVL* 0 0 R/W R/W P11/AEVL/FTCI/IRQ1 Pin Function Switch 00: P11 I/O pin 01: AEVL input pin 1x: FTCI input pin
Rev. 3.00 May 15, 2007 Page 121 of 516 REJ09B0152-0300
Section 8 I/O Ports
Bit 2 1 0
Bit Name CLKOUT TMOW AEVH
Initial Value 0 0 0
R/W R/W R/W R/W
Description P10/AEVH/FTIOA/TMOW/CLKOUT Pin Function Switch 000: P10 I/O pin and FTIOA I/O pin 001: AEVH input pin 01x: TMOW pin 100: CLKOUT output pin (OSC) 101: CLKOUT output pin (OSC/2) 110: CLKOUT output pin (OSC/4) 111: Setting prohibited
[Legend] Note: *
x: Don't care. When the IRQ1S1 and IRQ1S0 bits in PFCR are set to B'10, the pin function becomes the IRQ1 input pin regardless of the setting of these bits.
8.1.5
Pin Functions
The relationship between the register settings and the port functions is shown below. * P12/IRQAEC/AECPWM pin
Register Name Bit Name Setting PMR1 IRQAEC 0 AEGSR ECPWME x PCR1 PCR12 0 1 1 [Legend] x: Don't care. 1 0 x x P12 input pin P12 output pin AECPWM output pin IRQAEC input pin Pin Function
Rev. 3.00 May 15, 2007 Page 122 of 516 REJ09B0152-0300
Section 8 I/O Ports
* P11/AEVL/FTCI (/IRQ1) pin
Register Name Bit Name Setting PFCR IRQ1S1 and IRQ1S0 Other than B'10 PMR1 FTCI 0 AEVL 0 PCR1 PCR11 0 1 1 1 B'10 [Legend] x: Don't care. x x x x x x P11 input pin P11 output pin AEVL input pin FTCI input pin IRQ1 input pin Pin Function
* P10/AEVH/FTIOA/TMOW/CLKOUT pin
Register Name Bit Name Setting PMR1 TIOR0 PCR1 Pin Function
CLKOUT TMOW AEVH IOA2 IOA1 IOA0 PCR10 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 x 0 1 1 0 x x x x x x x x x x x x 0 x x x x x x x x x 0 1 x x x x x P10 input pin P10 output pin FTIOA output pin FTIOA output pin P10 input/FTIOA input pin P10 output/FTIOA input pin AEVH input pin TMOW pin CLKOUT output pin (OSC)* CLKOUT output pin (OSC/2)* CLKOUT output pin (OSC/4)*
[Legend] Note: *
x: Don't care. Switching the clock (OSC, OSC/2, or OSC/4) for CLKOUT output must be performed when CLKOUT output is halted (CLKOUT = 0). When making a transition to a power-down mode wherein the system clock oscillator is halted, the output level is retained. (In standby mode, output is the high-impedance state.) When making a transition from a power-down mode wherein the system clock oscillator is halted, to the active mode wherein the system clock oscillator operates, halt CLKOUT output (CLKOUT = 0) before the transition.
Rev. 3.00 May 15, 2007 Page 123 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.1.6
Input Pull-Up MOS
Port 1 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 2 to 0) PCR1n PUCR1n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off
8.2
Port 3
Port 3 is an I/O port also functioning as an SCI3/IrDA I/O pin, comparator reference voltage pin and interrupt pin. Figure 8.2 shows its pin configuration.
P32/TXD3/IrTXD
Port 3
P31/RXD3/IrRXD P30/SCK3/VCref (/IRQ0)
Figure 8.2 Port 3 Pin Configuration Port 3 has the following registers. * * * * Port data register 3 (PDR3) Port control register 3 (PCR3) Port pull-up control register 3 (PUCR3) Port mode register 3 (PMR3)
Rev. 3.00 May 15, 2007 Page 124 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.2.1
Port Data Register 3 (PDR3)
PDR3 is a register that stores data of port 3.
Bit 7 to 3 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 2 1 0 P32 P31 P30 0 0 0 R/W R/W R/W If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
8.2.2
Port Control Register 3 (PCR3)
PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3.
Bit 7 to 3 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 2 1 0 PCR32 PCR31 PCR30 0 0 0 W W W Setting a PCR3 bit to 1 makes the corresponding pin (P32 to P30) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid when the corresponding pin is designated as a general I/O pin. PCR3 is a write-only register. The read value is undefined.
Rev. 3.00 May 15, 2007 Page 125 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.2.3
Port Pull-Up Control Register 3 (PUCR3)
PUCR3 controls the pull-up MOS of the port 3 pins in bit units.
Bit 7 to 3 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 2 1 0 PUCR32 PUCR31 PUCR30 0 0 0 R/W R/W R/W When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
8.2.4
Port Mode Register 3 (PMR3)
PMR3 controls the selection of functions for port 3 pins.
Bit 7 to 1 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 0 VCref 0 R/W P30/SCK3/VCref Pin Function Switch 0: P30 and SCK3 I/O pin 1: Comparator reference voltage (VCref) pin
Rev. 3.00 May 15, 2007 Page 126 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.2.5
Pin Functions
The relationship between the register settings and the port functions is shown below. * P32/TXD3/IrTXD pin
Register Name Bit Name Setting SPCR SPC3 0 1 [Legend] x: Don't care. IrCR IrE x 0 1 PCR3 PCR32 0 1 x x Pin Function P32 input pin P32 output pin TXD3 output pin IrTXD output pin
* P31/RXD3/IrRXD pin
Register Name Bit Name Setting SCR3 RE 0 1 [Legend] x: Don't care. IrCR IrE x 0 1 PCR3 PCR31 0 1 x x P31 input pin P31 output pin RXD3 input pin IrRXD input pin Pin Function
* P30/SCK3/VCref (/IRQ0) pin
Register Name Bit Name Setting PFCR IRQ0S1 and IRQ0S0 Other than B'10 PMR3 VCref 0 SCR3 CKE1 CKE0 0 0 SMR3 PCR3 Pin Function COM PCR30 0 1 x x x x 0 1 x x x x x P30 input pin P30 output pin SCK3 output pin SCK3 output pin SCK3 input pin VCref pin IRQ0 input pin
[Legend]
B'10 x: Don't care.
1 x
1 x x
1 0 x x
Rev. 3.00 May 15, 2007 Page 127 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.2.6
Input Pull-Up MOS
Port 3 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 2 to 0) PCR3n PUCR3n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off
8.3
Port 8
Port 8 is an I/O port also functioning as a timer W I/O pin. Figure 8.3 shows its pin configuration.
P84/FTIOD
Port 8
P83/FTIOC P82/FTIOB
Figure 8.3 Port 8 Pin Configuration Port 8 has the following registers. * Port data register 8 (PDR8) * Port control register 8 (PCR8) * Port pull-up control register 8 (PUCR8)
Rev. 3.00 May 15, 2007 Page 128 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.3.1
Port Data Register 8 (PDR8)
PDR8 is a register that stores data of port 8.
Bit 7 to 5 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 4 3 2 1, 0 P84 P83 P82 0 0 0 R/W R/W R/W If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. Reserved The read value is undefined. These bits cannot be modified.
8.3.2
Port Control Register 8 (PCR8)
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit 7 to 5 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 4 3 2 PCR84 PCR83 PCR82 0 0 0 W W W Setting a PCR8 bit to 1 makes the corresponding pin (P84 to P82) an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR8 and in PDR8 are valid when the corresponding pin is designated as a general I/O pin. PCR8 is a write-only register. The read value is undefined. 1, 0 Reserved The read value is undefined. These bits cannot be modified.
Rev. 3.00 May 15, 2007 Page 129 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.3.3
Port Pull-Up Control Register 8 (PUCR8)
PUCR8 controls the pull-up MOS of the port 8 pins in bit units.
Bit 7 to 5 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 4 3 2 1, 0 PUCR84 PUCR83 PUCR82 0 0 0 R/W R/W R/W When a PCR8 bit is cleared to 0, setting the corresponding PUCR8 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS. Reserved The read value is undefined. These bits cannot be modified.
8.3.4
Pin Functions
The relationship between the register settings and the port functions is shown below. * P84/FTIOD pin
Register Name Bit Name Setting TMRW PWMD 0 IOD2 0 TIOR1 IOD1 0 IOD0 0 PCR8 PCR84 0 1 1 1 1 x x x x x 0 1 1 [Legend] x: Don't care. x x x x P84 input pin P84 output pin FTIOD output pin FTIOD output pin P84 input/FTIOD input pin P84 output/FTIOD input pin FTIOD output pin Pin Function
Rev. 3.00 May 15, 2007 Page 130 of 516 REJ09B0152-0300
Section 8 I/O Ports
* P83/FTIOC pin
Register Name Bit Name Setting TMRW PWMC 0 IOC2 0 TIOR1 IOC1 0 IOC0 0 1 1 1 x x x PCR8 PCR83 0 1 x x 0 1 1 [Legend] x: Don't care. x x x x P83 input pin P83 output pin FTIOC output pin FTIOC output pin P83 input/FTIOC input pin P83 output/FTIOC input pin FTIOC output pin Pin Function
* P82/FTIOB pin
Register Name Bit Name Setting TMRW PWMB 0 IOB2 0 TIOR0 IOB1 0 IOB0 0 PCR8 PCR82 0 1 1 1 1 x x x x x 0 1 1 [Legend] x: Don't care. x x x x P82 input pin P82 output pin FTIOB output pin FTIOB output pin P82 input/FTIOB input pin P82 output/FTIOB input pin FTIOB output pin Pin Function
Rev. 3.00 May 15, 2007 Page 131 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.3.5
Input Pull-Up MOS
Port 8 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR8 bit is cleared to 0, setting the corresponding PUCR8 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 4 to 2) PCR8n PUCR8n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off
8.4
Port 9
Port 9 is an I/O port also functioning as an SSU I/O pin, IIC2 I/O pin and interrupt pin. Figure 8.4 shows its pin configuration.
P93/SSI (IRQ1)
P93/SCS (IRQ1)
Port 9
P91/SSCK/SDA P90/SCS/SCL
Port 9
P92/SSO (IRQ0)
P92/SSCK (IRQ0) P91/SSO/SDA
P90/SSI/SCL
(1) SSUS = 0
(2) SSUS = 1
Figure 8.4 Port 9 Pin Configuration Port 9 has the following registers. * * * * Port data register 9 (PDR9) Port control register 9 (PCR9) Port open-drain control register 9 (PODR9) Port pull-up control register 9 (PUCR9)
Rev. 3.00 May 15, 2007 Page 132 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.4.1
Port Data Register 9 (PDR9)
PDR9 is a register that stores data of port 9.
Bit 7 to 4 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 3 2 1 0 P93 P92 P91 P90 0 0 0 0 R/W R/W R/W R/W If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read.
8.4.2
Port Control Register 9 (PCR9)
PCR9 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 9.
Bit 7 to 4 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 3 2 1 0 PCR93 PCR92 PCR91 PCR90 0 0 0 0 W W W W Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and in PDR9 are valid when the corresponding pin is designated as a general I/O pin. PCR9 is a write-only register. The read value is undefined.
Rev. 3.00 May 15, 2007 Page 133 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.4.3
Port Open-Drain Control Register 9 (PODR9)
PODR9 selects the output format for port 9 pins.
Bit 7 to 4 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 3 2 1 0 P93ODR P92ODR P91ODR P90ODR 0 0 0 0 R/W R/W R/W R/W When a bit among the P93ODR to P90ODR bits is set to 1, the corresponding pin among P93 to P90 functions as the NMOS open-drain output. When cleared to 0, the corresponding pin functions as the CMOS output.
8.4.4
Port Pull-Up Control Register 9 (PUCR9)
PUCR9 controls the pull-up MOS of the port 9 pins in bit units.
Bit 7 to 4 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 3 2 1 0 PUCR93 PUCR92 PUCR91 PUCR90 0 0 0 0 R/W R/W R/W R/W When a PCR9 bit is cleared to 0, setting the corresponding PUCR9 bit to 1 turns on the pull-up MOS for the corresponding pin, while clearing the bit to 0 turns off the pull-up MOS.
Rev. 3.00 May 15, 2007 Page 134 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.4.5
Pin Functions
The relationship between the register settings and the port functions is shown below. Note on the followings when port 9 is used. 1. When IIC is used, SSU should not be set. 2. When SSU is used, the ICE bit in IIC should be set to 0. 3. The port corresponding to the pins for SSU communication data (SSI and SSO) should not be set. 4. When the pins for communication data (SSI and SSO) are set to open-drain output with the SOOS bit in the SSCRH register of SSU, they are set to open-drain output regardless of the TE and RE bit settings in the SSER register. * P93/SSI (/IRQ1) pin
Register Name Bit Name Setting IRQ1S1 and IRQ1S0 Other than B'01 PFCR SSUS x PCR9 PCR93 0 1 0 1 B'01 x x x x P93 input pin P93 output pin SSI I/O pin SCS I/O pin IRQ1 input pin Pin Function
[Legend] x: Don't care. Note: When this pin is used as the SSI/SCS pin, register settings of the SSU are required. For details, see section 15.4.4, Communication Modes and Pin Functions, and appendix B.3, Port 9 Related Register Settings and Pin Functions.
Rev. 3.00 May 15, 2007 Page 135 of 516 REJ09B0152-0300
Section 8 I/O Ports
* P92/SSO (/IRQ0) pin
Register Name Bit Name Setting IRQ0S1 and IRQ0S0 Other than B'01 PFCR SSUS x PCR9 PCR92 0 1 0 1 B'01 x x x x P92 input pin P92 output pin SSO I/O pin SSCK I/O pin IRQ0 input pin Pin Function
[Legend] x: Don't care. Note: When this pin is used as the SSO/SSCK pin, register settings of the SSU are required. For details, see section 15.4.4, Communication Modes and Pin Functions, and appendix B.3, Port 9 Related Register Settings and Pin Functions.
* P91/SSCK/SDA pin
Register Name Bit Name Setting PFCR SSUS x PCR9 PCR91 0 1 0 1 x x x x P91 input pin P91 output pin SSCK I/O pin SSO I/O pin SDA I/O pin Pin Function
[Legend] x: Don't care. Note: When this pin is used as the SSO/SSCK pin, register settings of the SSU are required. For details, see section 15.4.4, Communication Modes and Pin Functions, and appendix B.3, Port 9 Related Register Settings and Pin Functions. When this pin is used as the SDA pin, 2 register settings of the IIC2 are required. For details, see section 16.3.1, I C Bus Control Register 1 (ICCR1). Note that the priority when pin functions conflict is SSU pin > IIC2 pin > P91.
Rev. 3.00 May 15, 2007 Page 136 of 516 REJ09B0152-0300
Section 8 I/O Ports
* P90/SCS/SCL pin
Register Name Bit Name Setting PFCR SSUS x PCR9 PCR90 0 1 0 1 x x x x P90 input pin P90 output pin SCS I/O pin SSI I/O pin SCL I/O pin Pin Function
[Legend] x: Don't care. Note: When this pin is used as the SCS/SSI pin, register settings of the SSU are required. For details, see section 15.4.4, Communication Modes and Pin Functions, and appendix B.3, Port 9 Related Register Settings and Pin Functions. When this pin is used as the SCL pin, 2 register settings of the IIC2 are required. For details, see section 16.3.1, I C Bus Control Register 1 (ICCR1). Note that the priority when pin functions conflict is SSU pin > IIC2 pin > P90.
8.4.6
Input Pull-Up MOS
Port 9 has an on-chip input pull-up MOS function that can be controlled by software. When a PCR9 bit is cleared to 0, setting the corresponding PUCR9 bit to 1 turns on the input pull-up MOS for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 3 to 0) PCR9n PUCR9n Input Pull-Up MOS [Legend] x: Don't care. 0 Off 0 1 On 1 x Off
Rev. 3.00 May 15, 2007 Page 137 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.5
Port B
Port B is an input-only port also functioning as an interrupt input pin, analog input pin, and comparator pin. Figure 8.5 shows its pin configuration.
PB5/AN5/COMP1 PB4/AN4/COMP0
Port B
PB3/AN3 PB2/AN2 PB1/AN1/IRQ1 PB0/AN0/IRQ0
Figure 8.5 Port B Pin Configuration Port B has the following registers. * Port data register B (PDRB) * Port mode register B (PMRB) 8.5.1 Port Data Register B (PDRB)
PDRB is a register that stores data of port B.
Bit 7, 6 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 5 4 3 2 1 0 PB5 PB4 PB3 PB2 PB1 PB0 Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel by the CH3 to CH0 bits in AMR of the A/D converter, that pin is read as 0 regardless of the input voltage.
Rev. 3.00 May 15, 2007 Page 138 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.5.2
Port Mode Register B (PMRB)
PMRB controls the selection of the port B pin functions.
Bit 7 to 4 Bit Name Initial Value R/W Description Reserved The read value is undefined. These bits cannot be modified. 3 ADTSTCHG 0 R/W TEST/ADTRG Pin Function Switch Selects whether pin TEST/ADTRG is used as TEST or as ADTRG. 0: TEST pin 1: ADTRG input pin For details on the setting of the ADTRG input pin, refer to section 17.4.2, External Trigger Input Timing. 2 Reserved The read value is undefined. This bit cannot be modified. 1 IRQ1 0 R/W PB1/AN1/IRQ1 Pin Function Switch Selects whether pin PB1/AN1/IRQ1 is used as PB1/AN1 or as IRQ1. 0: PB1/AN1 input pin 1: IRQ1 input pin* 0 IRQ0 0 R/W PB0/AN0/IRQ0 Pin Function Switch Selects whether pin PB0/AN0/IRQ0 is used as PB0/AN0 or as IRQ0. 0: PB0/AN0 input pin 1: IRQ0 input pin* Note: * When the IRQnS1 and IRQnS0 (n = 1 or 0) bits in PFCR are set to a value other than B'00, these bits should not be set since the IRQn pin is assigned to another port.
Rev. 3.00 May 15, 2007 Page 139 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.5.3
Pin Functions
The relationship between the register settings and the port functions is shown below. * PB5/AN5/COMP1 pin
Register Name Bit Name Setting [Legend] AMR CH3 to CH0 Other than B'1001 B'1001 x: Don't care. PB5/COMP1 input pin AN5 input pin Pin Function
* PB4/AN4/COMP0 pin
Register Name Bit Name Setting [Legend] AMR CH3 to CH0 Other than B'1000 B'1000 x: Don't care. PB4/COMP0 input pin AN4 input pin Pin Function
* PB3/AN3 pin
Register Name Bit Name Setting [Legend] AMR CH3 to CH0 Other than B'0111 B'0111 x: Don't care. PB3 input pin AN3 input pin Pin Function
* PB2/AN2 pin
Register Name Bit Name Setting [Legend] AMR CH3 to CH0 Other than B'0110 B'0110 x: Don't care. PB2 input pin AN2 input pin Pin Function
Rev. 3.00 May 15, 2007 Page 140 of 516 REJ09B0152-0300
Section 8 I/O Ports
* PB1/AN1/IRQ1 pin
Register Name Bit Name Setting PMRB IRQ1 0 AMR CH3 to CH0 Other than B'0101 B'0101 1 B'xxxx PFCR IRQ1S1 and IRQ1S0 B'xx B'xx B'00 Other than B'00 [Legend] x: Don't care. PB1 input pin AN1 input pin IRQ1 input pin Setting prohibited Pin Function
* PB0/AN0/IRQ0 pin
Register Name Bit Name Setting PMRB IRQ0 0 AMR CH3 to CH0 Other than B'0100 B'0100 1 B'xxxx PFCR IRQ0S1 and IRQ0S0 B'xx B'xx B'00 Other than B'00 [Legend] x: Don't care. PB0 input pin AN0 input pin IRQ0 input pin Setting prohibited Pin Function
Rev. 3.00 May 15, 2007 Page 141 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.6
8.6.1
Input/Output Data Inversion
Serial Port Control Register (SPCR)
SPCR switches input/output data inversion of the RXD3 (IrRXD) and TXD3 (IrTXD) pins.
SCINV0 RXD3/IrRXD P31/RXD3/IrRXD
SCINV1
P32/TXD3/IrTXD
TXD3/IrTXD
Figure 8.6 Input/Output Data Inversion Function
Bit 7 to 5 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 4 SPC3 0 R/W P32/TXD3/IrTXD Pin Function Switch Selects whether pin P32/TXD3/IrTXD is used as P32 or as TXD3/IrTXD. 0: P32 I/O pin 1: TXD3/IrTXD output pin* Note: * Set the TE bit in SCR3 after setting this bit to 1. 3, 2 All 0 Reserved These bits are always read as 0 and cannot be modified. 1 SCINV1 0 R/W TXD3/IrTXD Pin Output Data Inversion Switch Specifies whether the logic level of output data of the TXD3/IrTXD pin is to be inverted or not. 0: TXD3/IrTXD output data is not inverted 1: TXD3/IrTXD output data is inverted
Rev. 3.00 May 15, 2007 Page 142 of 516 REJ09B0152-0300
Section 8 I/O Ports
Bit 0
Bit Name SCINV0
Initial Value 0
R/W R/W
Description RXD3/IrRXD Pin Input Data Inversion Switch Specifies whether the logic level of input data of the RXD3/IrRXD pin is to be inverted or not. 0: RXD3/IrRXD input data is not inverted 1: RXD3/IrRXD input data is inverted
Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated.
8.6.2
Port Function Control Register (PFCR)
PFCR changes the SSU pin assignments, and assigns the IRQ0 and IRQ1 input pins to other ports.
Bit 7 to 5 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0. These bits cannot be modified. SSU Pin Select Changes the SSU pin assignments. 0: SSI is assigned to P93 SSO is assigned to P92 SSCK is assigned to P91 SCS is assigned to P90 1: SSI is assigned to P90 SSO is assigned to P91 SSCK is assigned to P92 SCS is assigned to P93 IRQ1 Select 1, 0 00: IRQ1 is input from PB1 01: IRQ1 is input from P93 10: IRQ1 is input from P11 11: Setting prohibited IRQ0 Select 1, 0 00: IRQ0 is input from PB0 01: IRQ0 is input from P92 10: IRQ0 is input from P30 11: Setting prohibited
4
SSUS
0
R/W
3 2
IRQ1S1 IRQ1S0
0 0
R/W R/W
1 0
IRQ0S1 IRQ0S0
0 0
R/W R/W
Rev. 3.00 May 15, 2007 Page 143 of 516 REJ09B0152-0300
Section 8 I/O Ports
8.7
8.7.1
Usage Notes
How to Handle Unused Pin
If an I/O pin not used by the user system is floating, pull it up or down. * If an unused pin is an input pin, handle it in one of the following ways: Pull it up to Vcc with an on-chip pull-up MOS. Pull it up to Vcc with an external resistor of approximately 100 k. Pull it down to Vss with an external resistor of approximately 100 k. For a pin also used by the A/D converter, pull it up to AVcc with an external resistor of approximately 100 k. * If an unused pin is an output pin, handle it in one of the following ways: Set the output of the unused pin to high and pull it up to Vcc with an external resistor of approximately 100 k. Set the output of the unused pin to low and pull it down to GND with an external resistor of approximately 100 k. 8.7.2 Input Characteristics Difference due to Pin Function
When the functions of pins IRQ0, IRQ1, IRQAEC, AEVL, AEVH, SCK3, FTIOA to FTIOD, FTCI, SSCK, SCS, SDA, and SCL are selected, the corresponding pins have the schmitt-trigger input characteristics, which are different from the ones when they are used as the port input pins. For example, the input high voltage and the input low voltage of the PB0/AN0/IRQ0 pin differ when the pin is used as PB0 input or IRQ0 input. For details, refer to table 21.2 which lists the DC characteristics for F-ZTAT version, and table 21.13 which lists the DC characteristics for masked ROM version.
Rev. 3.00 May 15, 2007 Page 144 of 516 REJ09B0152-0300
Section 9 Timer B1
Section 9 Timer B1
Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 9.1 shows a block diagram of timer B1.
9.1
Features
* Selection of eight internal clock sources (/8192, /2048, /256, /64, /16, /4, W/1024, and W/256). * An interrupt is generated when the counter overflows. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (Timer B1 is halted as the initial value. For details, refer to section 5.4, Module Standby Function.)
TMB1
TCB1 w 1/4 w/4 PSW [w/1024, w/256] TLB1
[Legend] TMB1: TCB1: TLB1: IRRTB1: PSS: PSW: Timer mode register B1 Timer counter B1 Timer load register B1 Time B1 interrupt request flag Prescaler S Prescaler W IRRTB1
Figure 9.1 Block Diagram of Timer B1
Rev. 3.00 May 15, 2007 Page 145 of 516 REJ09B0152-0300
Internal data bus
PSS
Section 9 Timer B1
9.2
Register Descriptions
Timer B1 has the following registers. * Timer mode register B1 (TMB1) * Timer counter B1 (TCB1) * Timer load register B1 (TLB1) 9.2.1 Timer Mode Register B1 (TMB1)
TMB1 selects the auto-reload function and input clock.
Bit 7 Bit Name TMB17 Initial Value 0 R/W R/W Description Auto-Reload Function Select 0: Interval timer function selected 1: Auto-reload function selected 6 TMB16 0 R/W Counter Operation/Stop Select 0: Counter stopped 1: Counter operates 5 to 3 2 1 0 TMB12 TMB11 TMB10 All 1 0 0 0 R/W R/W R/W Reserved These bits are always read as 1. Counter Clock Select 000: Internal clock: /8192 001: Internal clock: /2048 010: Internal clock: /256 011: Internal clock: /64 100: Internal clock: /16 101: Internal clock: /4 110: Internal clock: W/1024 111: Internal clock: W/256
Rev. 3.00 May 15, 2007 Page 146 of 516 REJ09B0152-0300
Section 9 Timer B1
9.2.2
Timer Counter B1 (TCB1)
TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1 is initialized to H'00. 9.2.3 Timer Load Register B1 (TLB1)
TLB1 is an 8-bit write-only register for setting the reload value of TCB1. Setting the reload value to TLB1 must be done when bit TMB16 in TMB1 is cleared to 0. When a reload value is set in TLB1, the same value is loaded into TCB1 as well, and TCB1 starts counting up from that value. When TCB1 overflows during operation in auto-reload mode, the TLB1 value is loaded into TCB1. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. TLB1 is allocated to the same address as TCB1. TLB1 is initialized to H'00.
Rev. 3.00 May 15, 2007 Page 147 of 518 REJ09B0152-0300
Section 9 Timer B1
9.3
Usage Method
Figure 9.2 shows the initial setting flow of timer B1 after a reset, and figure 9.3 shows the processing flow for changing a setting during counter operation. Bit TMB16 in TMB1 must be cleared to 0 when setting timer B1, as shown in the figures. Operation is not guaranteed when a setting is made with bit TMB16 in TMB1 set to 1.
Cancel the module standby mode of timer B1 *1 Set counter function with bit TMB17 in TMB1 and counter clock with bits TMB12 to TMB10 in TMB1 (bit TMB16 must be cleared to 0 when writing to these bits)
Set reload value to TLB1 when auto-reload function is selected
Set bit TMB16 in TMB1 to 1 to start counter operation (bits other than TMB16 must have the same values set at *1)
Figure 9.2 Timer B1 Initial Setting Flow
Rev. 3.00 May 15, 2007 Page 148 of 516 REJ09B0152-0300
Section 9 Timer B1
Clear bit TMB16 in TMB1 to 0 to stop counter operation *2 To modify the counter clock, change the value in bits TMB12 to TMB10 in TMB1 (bit TMB16 must be cleared to 0 when writing to these bits)
To change the reload value, set a new reload value in TLB1
Set bit TMB16 in TMB1 to 1 to start counter operation (bits other than TMB16 must have the same values set at *2)
Figure 9.3 Processing Flow When Changing Setting during Counter Operation
Rev. 3.00 May 15, 2007 Page 149 of 518 REJ09B0152-0300
Section 9 Timer B1
9.4
9.4.1
Operation
Interval Timer Operation
When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so the interval timer function is selected immediately after a reset. The operating clock of timer B1 is selected from eight internal clock signals output by prescaler S or prescaler W. The selection is made by bits TMB12 to TMB10 in TMB1. After bit TMB16 in TMB1 is set to 1 to start the counter operation and the count value in TMB1 reaches H'FF, the next clock signal input causes timer B1 to overflow, setting flag IRRTB1 in IRR2 to 1. If IENTB1 in IENR2 is 1, an interrupt is requested to the CPU. At overflow, TCB1 returns to H'00 and starts counting up again. Even though interval timer operation (TMB17 = 0) is selected, when a value is set in TLB1 with bit TMB16 in TMB1 cleared to 0, the same value is set in TCB1. 9.4.2 Auto-Reload Timer Operation
Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1 with bit TMB16 in TMB1 cleared to 0, the same value is loaded into TCB1. After bit TMB16 in TMB1 is set to 1 to start the counter operation and the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value. The overflow period can be set within a range from 1 to 256 input clocks, depending on the TLB1 value. The clock sources and interrupts in auto-reload mode are the same as in interval mode. To set a new value in TLB1 in auto-reload mode (TMB17 = 1), clear bit TMB16 in TMB1 to 0 before making the new setting.
Rev. 3.00 May 15, 2007 Page 150 of 516 REJ09B0152-0300
Section 9 Timer B1
9.5
Timer B1 Operating Modes
Table 9.1 shows the timer B1 operating modes. Table 9.1 Timer B1 Operating Modes
Active Sleep Oscillation Stabilization Time Subsleep Watch Clock Source Highspeed Mediumspeed HighMediumSubWatch active Subsleep Standby Standby to Active to Active to Active speed speed
w/256, w/1024 /4, /16, /64, /256, /2048, /8192

x
x
x
x x
x x
x
x
[Legend]
: Counting enabled x: Counting disabled (Counter value retained)
Rev. 3.00 May 15, 2007 Page 151 of 518 REJ09B0152-0300
Section 9 Timer B1
Rev. 3.00 May 15, 2007 Page 152 of 516 REJ09B0152-0300
Section 10 Timer W
Section 10 Timer W
The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems.
10.1
Features
* Selection of eight counter clock sources: seven internal clocks (, /2, /4, /8, W, W/4, and W/16) and an external clock (external events can be counted) * Capability to process up to four pulse outputs or four pulse inputs * Four general registers: Independently assignable output compare or input capture functions Usable as two pairs of registers; one register of each pair operates as a buffer for the output compare or input capture register * Four selectable operating modes: Waveform output by compare match Selection of 0 output, 1 output, or toggle output Input capture function Rising edge, falling edge, or both edges Counter clearing function Counters can be cleared by compare match PWM mode Up to three-phase PWM output can be provided with desired duty ratio. * Any initial timer output value can be set * Five interrupt sources Four compare match/input capture interrupts and an overflow interrupt. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (The timer W is halted as the initial value. For details, refer to section 5.4, Module Standby Function.) Table 10.1 summarizes the timer W functions, and figure 10.1 shows a block diagram of the timer W.
TIM08W0A_000020020200
Rev. 3.00 May 15, 2007 Page 153 of 516 REJ09B0152-0300
Section 10 Timer W
Table 10.1 Timer W Functions
Input/Output Pins Item Count clock General registers (output compare/input capture registers) Counter clearing function Counter FTIOA FTIOB FTIOC FTIOD Internal clocks: , /2, /4, /8, W, W/4, and W/16 External clock: FTCI Period GRA specified in GRA GRA compare match -- -- 0 1 Toggle Input capture function PWM mode Interrupt sources -- -- -- -- -- Overflow GRA compare match Yes Yes Yes Yes Yes Yes -- Compare match/input capture GRB GRC (buffer register for GRA in buffer mode) -- GRD (buffer register for GRB in buffer mode) --
--
Initial output value setting function Buffer function Compare match output
Yes Yes Yes Yes Yes Yes Yes Compare match/input capture
Yes -- Yes Yes Yes Yes Yes Compare match/input capture
Yes -- Yes Yes Yes Yes Yes Compare match/input capture
Rev. 3.00 May 15, 2007 Page 154 of 516 REJ09B0152-0300
Section 10 Timer W
Internal clock: /2 /4 /8 W W/4 W/16 External clock: FTCI
FTIOA Clock selector Control logic Comparator FTIOB FTIOC FTIOD IRRTW
TIERW
TMRW
TCRW
TSRW
TCNT
TIOR
GRC
GRD
GRA
GRB
[Legend] TMRW: TCRW: TIERW: TSRW: TIOR: TCNT: GRA: GRB: GRC: GRD: IRRTW:
Timer mode register W (8 bits) Timer control register W (8 bits) Timer interrupt enable register W (8 bits) Timer status register W (8 bits) Timer I/O control register (8 bits) Timer counter (16 bits) General register A (input capture/output compare register: 16 bits) General register B (input capture/output compare register: 16 bits) General register C (input capture/output compare register: 16 bits) General register D (input capture/output compare register: 16 bits) Timer W interrupt request
Figure 10.1 Timer W Block Diagram
Rev. 3.00 May 15, 2007 Page 155 of 518 REJ09B0152-0300
Bus interface
Internal data bus
Section 10 Timer W
10.2
Input/Output Pins
Table 10.2 shows the pin configuration of the timer W. Table 10.2 Pin Configuration
Name External clock input Input capture/output compare A Input capture/output compare B Input capture/output compare C Input capture/output compare D Abbreviation FTCI FTIOA FTIOB Input/Output Input Input/output Input/output Function External clock input pin Output pin for GRA output compare or input pin for GRA input capture Output pin for GRB output compare, input pin for GRB input capture, or PWM output pin in PWM mode Output pin for GRC output compare, input pin for GRC input capture, or PWM output pin in PWM mode Output pin for GRD output compare, input pin for GRD input capture, or PWM output pin in PWM mode
FTIOC
Input/output
FTIOD
Input/output
10.3
Register Descriptions
The timer W has the following registers. * * * * * * * * * * * Timer mode register W (TMRW) Timer control register W (TCRW) Timer interrupt enable register W (TIERW) Timer status register W (TSRW) Timer I/O control register 0 (TIOR0) Timer I/O control register 1 (TIOR1) Timer counter (TCNT) General register A (GRA) General register B (GRB) General register C (GRC) General register D (GRD)
Rev. 3.00 May 15, 2007 Page 156 of 516 REJ09B0152-0300
Section 10 Timer W
10.3.1
Timer Mode Register W (TMRW)
TMRW selects the general register functions and the timer output mode.
Bit 7 Bit Name CTS Initial Value 0 R/W R/W Description Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 5 BUFEB 1 0 R/W Reserved This bit is always read as 1. Buffer Operation B Selects the GRD function. 0: GRD operates as an input capture/output compare register 1: GRD operates as the buffer register for GRB 4 BUFEA 0 R/W Buffer Operation A Selects the GRC function. 0: GRC operates as an input capture/output compare register 1: GRC operates as the buffer register for GRA 3 2 PWMD 1 0 R/W Reserved This bit is always read as 1. PWM Mode D Selects the output mode of the FTIOD pin. 0: FTIOD operates normally (output compare output) 1: PWM output 1 PWMC 0 R/W PWM Mode C Selects the output mode of the FTIOC pin. 0: FTIOC operates normally (output compare output) 1: PWM output 0 PWMB 0 R/W PWM Mode B Selects the output mode of the FTIOB pin. 0: FTIOB operates normally (output compare output) 1: PWM output
Rev. 3.00 May 15, 2007 Page 157 of 518 REJ09B0152-0300
Section 10 Timer W
10.3.2
Timer Control Register W (TCRW)
TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels.
Bit 7 Bit Name CCLR Initial Value 0 R/W R/W Description Counter Clear The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a freerunning counter. Clock Select 2 to 0 Select the TCNT clock source. 000: Internal clock: counts on 001: Internal clock: counts on /2 010: Internal clock: counts on /4 011: Internal clock: counts on /8 100: Internal clock: counts on W 101: Internal clock: counts on W/4 110: Internal clock: counts on W/16 111: Counts on rising edges of the external event (FTCI) With a setting of 0xx, the timer W can be used only in active mode or sleep mode. Do not make this setting in subactive mode or subsleep mode. When 100 is set in subactive mode or subsleep mode, the timer W can be used only when W is selected as the CPU operating clock. When 101 is set in subactive mode or subsleep mode, the timer W can be used only when W or W/2 is selected as the CPU operating clock. Timer Output Level Setting D Sets the output value of the FTIOD pin until the first compare match D is generated. 0: Output value is 0* 1: Output value is 1* Timer Output Level Setting C Sets the output value of the FTIOC pin until the first compare match C is generated. 0: Output value is 0* 1: Output value is 1*
6 5 4
CKS2 CKS1 CKS0
0 0 0
R/W R/W R/W
3
TOD
0
R/W
2
TOC
0
R/W
Rev. 3.00 May 15, 2007 Page 158 of 516 REJ09B0152-0300
Section 10 Timer W
Bit 1
Bit Name TOB
Initial Value 0
R/W R/W
Description Timer Output Level Setting B Sets the output value of the FTIOB pin until the first compare match B is generated. 0: Output value is 0* 1: Output value is 1*
0
TOA
0
R/W
Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1*
[Legend] Note: *
x: Don't care. The change of the setting is immediately reflected in the output value.
10.3.3
Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit 7 Bit Name OVIE Initial Value 0 R/W R/W Description Timer Overflow Interrupt Enable When this bit is set to 1, FOVI interrupt requested by OVF flag in TSRW is enabled. Reserved These bits are always read as 1. Input Capture/Compare Match Interrupt Enable D When this bit is set to 1, IMID interrupt requested by IMFD flag in TSRW is enabled. Input Capture/Compare Match Interrupt Enable C When this bit is set to 1, IMIC interrupt requested by IMFC flag in TSRW is enabled. Input Capture/Compare Match Interrupt Enable B When this bit is set to 1, IMIB interrupt requested by IMFB flag in TSRW is enabled. Input Capture/Compare Match Interrupt Enable A When this bit is set to 1, IMIA interrupt requested by IMFA flag in TSRW is enabled.
6 to 4 3
IMIED
All 1 0
R/W
2
IMIEC
0
R/W
1
IMIEB
0
R/W
0
IMIEA
0
R/W
Rev. 3.00 May 15, 2007 Page 159 of 518 REJ09B0152-0300
Section 10 Timer W
10.3.4
Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit 7 Bit Name OVF Initial Value 0 R/W R/(W)* Description Timer Overflow Flag [Setting condition] When TCNT overflows from H'FFFF to H'0000 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 to 4 3 IMFD All 1 0 R/(W)* Reserved These bits are always read as 1. Input Capture/Compare Match Flag D [Setting conditions] * * TCNT = GRD when GRD functions as an output compare register The TCNT value is transferred to GRD by an input capture signal when GRD functions as an input capture register
[Clearing condition] Read IMFD when IMFD = 1, then write 0 in IMFD 2 IMFC 0 R/(W)* Input Capture/Compare Match Flag C [Setting conditions] * * TCNT = GRC when GRC functions as an output compare register The TCNT value is transferred to GRC by an input capture signal when GRC functions as an input capture register
[Clearing condition] Read IMFC when IMFC = 1, then write 0 in IMFC
Rev. 3.00 May 15, 2007 Page 160 of 516 REJ09B0152-0300
Section 10 Timer W
Bit 1
Bit Name IMFB
Initial Value 0
R/W
Description
R/(W)* Input Capture/Compare Match Flag B [Setting conditions] * * TCNT = GRB when GRB functions as an output compare register The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register
[Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB 0 IMFA 0 R/(W)* Input Capture/Compare Match Flag A [Setting conditions] * * TCNT = GRA when GRA functions as an output compare register The TCNT value is transferred to GRA by an input capture signal when GRA functions as an input capture register
[Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA Note: * Only 0 can be written to clear the flag.
10.3.5
Timer I/O Control Register 0 (TIOR0)
TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and FTIOB pins.
Bit 7 6 Bit Name IOB2 Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1. I/O Control B2 Selects the GRB function. 0: GRB functions as an output compare register 1: GRB functions as an input capture register
Rev. 3.00 May 15, 2007 Page 161 of 518 REJ09B0152-0300
Section 10 Timer W
Bit 5 4
Bit Name IOB1 IOB0
Initial Value 0 0
R/W R/W R/W
Description I/O Control B1 and B0 When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1, 00: Input capture at rising edge at the FTIOB pin 01: Input capture at falling edge at the FTIOB pin 1x: Input capture at rising and falling edges of the FTIOB pin Reserved This bit is always read as 1. I/O Control A2 Selects the GRA function. 0: GRA functions as an output compare register 1: GRA functions as an input capture register I/O Control A1 and A0 When IOA2 = 0, 00: No output at compare match 01: 0 output to the FTIOA pin at GRA compare match 10: 1 output to the FTIOA pin at GRA compare match 11: Output toggles to the FTIOA pin at GRA compare match When IOA2 = 1, 00: Input capture at rising edge of the FTIOA pin 01: Input capture at falling edge of the FTIOA pin 1x: Input capture at rising and falling edges of the FTIOA pin
3 2
IOA2
1 0
R/W
1 0
IOA1 IOA0
0 0
R/W R/W
[Legend]
x: Don't care.
Rev. 3.00 May 15, 2007 Page 162 of 516 REJ09B0152-0300
Section 10 Timer W
10.3.6
Timer I/O Control Register 1 (TIOR1)
TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins.
Bit 7 6 Bit Name IOD2 Initial Value 1 0 R/W R/W Description Reserved This bit is always read as 1. I/O Control D2 Selects the GRD function. 0: GRD functions as an output compare register 1: GRD functions as an input capture register I/O Control D1 and D0 When IOD2 = 0, 00: No output at compare match 01: 0 output to the FTIOD pin at GRD compare match 10: 1 output to the FTIOD pin at GRD compare match 11: Output toggles to the FTIOD pin at GRD compare match When IOD2 = 1, 00: Input capture at rising edge at the FTIOD pin 01: Input capture at falling edge at the FTIOD pin 1x: Input capture at rising and falling edges at the FTIOD pin Reserved This bit is always read as 1. I/O Control C2 Selects the GRC function. 0: GRC functions as an output compare register 1: GRC functions as an input capture register
5 4
IOD1 IOD0
0 0
R/W R/W
3 2
IOC2
1 0
R/W
Rev. 3.00 May 15, 2007 Page 163 of 518 REJ09B0152-0300
Section 10 Timer W
Bit 1 0
Bit Name IOC1 IOC0
Initial Value 0 0
R/W R/W R/W
Description I/O Control C1 and C0 When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1x: Input capture to GRC at rising and falling edges of the FTIOC pin
[Legend]
x: Don't care.
10.3.7
Timer Counter (TCNT)
TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed. TCNT is initialized to H'0000 by a reset.
Rev. 3.00 May 15, 2007 Page 164 of 516 REJ09B0152-0300
Section 10 Timer W
10.3.8
General Registers A to D (GRA to GRD)
Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TIOR0 and TIOR1. When a general register is used as an output-compare register, its value is constantly compared with the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when IMIEA, IMIEB, IMIEC, or IMIED in TIERW is set to 1. Compare match output can be selected in TIOR. When a general register is used as an input-capture register, an external input-capture signal is detected and the current TCNT value is stored in the general register. The corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit (IMIEA, IMIEB, IMIEC, or IMIED) in TIERW is set to 1 at this time, an interrupt request is generated. The edge of the input-capture signal is selected in TIOR. GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA and BUFEB in TMRW. For example, when GRA is set as an output-compare register and GRC is set as the buffer register for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is generated. When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the value in TCNT is transferred to GRA and the value in GRA is transferred to GRC whenever an input capture is generated. GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are initialized to H'FFFF by a reset.
Rev. 3.00 May 15, 2007 Page 165 of 518 REJ09B0152-0300
Section 10 Timer W
10.4
Operation
The timer W has the following operating modes. * Normal Operation * PWM Operation 10.4.1 Normal Operation
TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE in TIERW is set to 1, an interrupt request is generated. Figure 10.2 shows free-running counting.
TCNT value H'FFFF
H'0000 CTS bit
Time
Flag cleared by software
OVF
Figure 10.2 Free-Running Counter Operation
Rev. 3.00 May 15, 2007 Page 166 of 516 REJ09B0152-0300
Section 10 Timer W
Periodic counting operation can be performed when GRA is set as an output compare register and CCLR bit in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated. TCNT continues counting from H'0000. Figure 10.3 shows periodic counting.
TCNT value GRA
H'0000 CTS bit Flag cleared by software IMFA
Time
Figure 10.3 Periodic Counter Operation By setting a general register as an output compare register, compare match A, B, C, or D can cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure 10.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output is selected for compare match A, and 0 output is selected for compare match B. When signal is already at the selected output level, the signal level does not change at compare match.
TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB No change No change Time No change No change
Figure 10.4 0 and 1 Output Example (TOA = 0, TOB = 1)
Rev. 3.00 May 15, 2007 Page 167 of 518 REJ09B0152-0300
Section 10 Timer W
Figure 10.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B.
TCNT value H'FFFF GRA GRB H'0000 FTIOA FTIOB Time Toggle output Toggle output
Figure 10.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 10.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B.
TCNT value Counter cleared by compare match with GRA H'FFFF GRA GRB H'0000 FTIOA FTIOB Time Toggle output Toggle output
Figure 10.6 Toggle Output Example (TOA = 0, TOB = 1)
Rev. 3.00 May 15, 2007 Page 168 of 516 REJ09B0152-0300
Section 10 Timer W
The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured. Figure 10.7 shows an example of input capture when both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates as a free-running counter.
TCNT value
H'FFFF H'F000 H'AA55 H'55AA H'1000 H'0000
Time
FTIOA
GRA
H'1000
H'F000
H'55AA
FTIOB GRB H'AA55
Figure 10.7 Input Capture Operating Example
Rev. 3.00 May 15, 2007 Page 169 of 518 REJ09B0152-0300
Section 10 Timer W
Figure 10.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
TCNT value H'FFFF H'DA91 H'5480 H'0245 H'0000 FTIOA
Time
GRA GRC
H'0245
H'5480 H'0245
H'DA91 H'5480
Figure 10.8 Buffer Operation Example (Input Capture) 10.4.2 PWM Operation
In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically. The output level of each pin depends on the corresponding timer output level set bit (TOB, TOC, and TOD) in TCRW. When TOB is 1, the FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode. If the same value is set in the cycle register and the duty register, the output does not change when a compare match occurs. Figure 10.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 1: initial output values are set to 1).
Rev. 3.00 May 15, 2007 Page 170 of 516 REJ09B0152-0300
Section 10 Timer W
TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 FTIOB FTIOC Time
FTIOD
Figure 10.9 PWM Mode Example (1) Figure 10.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 0).
TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 FTIOB FTIOC Time
FTIOD
Figure 10.10 PWM Mode Example (2)
Rev. 3.00 May 15, 2007 Page 171 of 518 REJ09B0152-0300
Section 10 Timer W
Figure 10.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs.
TCNT value
GRA H'0200
H'0450
H'0520
GRB H'0000 GRD
Time H'0200 H'0450 H'0520
GRB
H'0200
H'0450
H'0520
FTIOB
Figure 10.11 Buffer Operation Example (Output Compare)
Rev. 3.00 May 15, 2007 Page 172 of 516 REJ09B0152-0300
Section 10 Timer W
Figures 10.12 and 10.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%.
TCNT value Write to GRB GRA
GRB H'0000 Duty 0%
Write to GRB Time
FTIOB TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB Write to GRB
GRB H'0000 Duty 100% Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB Write to GRB Time Duty 100% Duty 0%
GRB H'0000
FTIOB
Figure 10.12 PWM Mode Example (TOB, TOC, and TOD = 0: initial output values are set to 0)
Rev. 3.00 May 15, 2007 Page 173 of 518 REJ09B0152-0300
Section 10 Timer W
TCNT value GRA
Write to GRB
GRB H'0000 Duty 100%
Write to GRB Time
FTIOB TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB Write to GRB
GRB H'0000 Duty 0% Time
FTIOB
TCNT value Write to GRB GRA
Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB Write to GRB Time Duty 0% Duty 100%
GRB H'0000
FTIOB
Figure 10.13 PWM Mode Example (TOB, TOC, and TOD = 1: initial output values are set to 1)
Rev. 3.00 May 15, 2007 Page 174 of 516 REJ09B0152-0300
Section 10 Timer W
10.5
10.5.1
Operation Timing
TCNT Count Timing
Figure 10.14 shows the TCNT count timing when the internal clock source is selected. Figure 10.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock () cycles; shorter pulses will not be counted correctly.
Internal clock TCNT input clock TCNT
N
Rising edge
N+1
N+2
Figure 10.14 Count Timing for Internal Clock Source
External clock TCNT input clock TCNT N N+1
N+2
Rising edge
Rising edge
Figure 10.15 Count Timing for External Clock Source
Rev. 3.00 May 15, 2007 Page 175 of 518 REJ09B0152-0300
Section 10 Timer W
10.5.2
Output Compare Output Timing
The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next counter clock pulse is input. Figure 10.16 shows the output compare timing.
TCNT input clock TCNT
N N+1
GRA to GRD Compare match signal FTIOA to FTIOD
N
Figure 10.16 Output Compare Output Timing
Rev. 3.00 May 15, 2007 Page 176 of 516 REJ09B0152-0300
Section 10 Timer W
10.5.3
Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 10.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock () cycles; shorter pulses will not be detected correctly.
Input capture input Input capture signal TCNT GRA to GRD
N-1
N
N+1
N+2
N
Figure 10.17 Input Capture Input Signal Timing 10.5.4 Timing of Counter Clearing by Compare Match
Figure 10.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1.
Compare match signal
TCNT
N
H'0000
GRA
N
Figure 10.18 Timing of Counter Clearing by Compare Match
Rev. 3.00 May 15, 2007 Page 177 of 518 REJ09B0152-0300
Section 10 Timer W
10.5.5
Buffer Operation Timing
Figures 10.19 and 10.20 show the buffer operation timing.
Compare match signal TCNT N N+1
GRC, GRD
M
GRA, GRB
M
Figure 10.19 Buffer Operation Timing (Compare Match)
Input capture signal TCNT
N
N+1
GRA, GRB
M
N
N+1
GRC, GRD
M
N
Figure 10.20 Buffer Operation Timing (Input Capture)
Rev. 3.00 May 15, 2007 Page 178 of 516 REJ09B0152-0300
Section 10 Timer W
10.5.6
Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a general register, the compare match signal is generated only after the next TCNT clock pulse is input. Figure 10.21 shows the timing of the IMFA to IMFD flag setting at compare match.
TCNT input clock TCNT N N+1
GRA to GRD
Compare match signal
N
IMFA to IMFD
IRRTW
Figure 10.21 Timing of IMFA to IMFD Flag Setting at Compare Match
Rev. 3.00 May 15, 2007 Page 179 of 518 REJ09B0152-0300
Section 10 Timer W
10.5.7
Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 10.22 shows the timing of the IMFA to IMFD flag setting at input capture.
Input capture signal TCNT N
GRA to GRD
N
IMFA to IMFD
IRRTW
Figure 10.22 Timing of IMFA to IMFD Flag Setting at Input Capture 10.5.8 Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 10.23 shows the status flag clearing timing.
TSRW write cycle T1 T2
Address
TSRW address
Write signal
IMFA to IMFD
IRRTW
Figure 10.23 Timing of Status Flag Clearing by CPU
Rev. 3.00 May 15, 2007 Page 180 of 516 REJ09B0152-0300
Section 10 Timer W
10.6
Timer W Operating Modes
Table 10.3 shows the timer W operating modes. Table 10.3 Timer W Operating Modes
Active Clock Source FTCI w, w/4, w/16 , /2, /4, /8 x x x x x x x HighMediumHighspeed Sleep Mediumspeed SubWatch active x x Subsleep Oscillation Stabilization Time Standby to Subsleep to Watch to Standby Active x x x x Active x x Active x x
speed speed
[Legend]
: Counting enabled x: Counting disabled (Counter value retained)
10.7
Usage Notes
The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock cycles; shorter pulses will not be detected correctly. The system clock described here indicates the clock set for the CPU operation. For example, in the w/8 operation, at least w x 16 clock cycles are required as the pulse width. 2. Writing to registers is performed in the T2 state of a TCNT write cycle. If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed, as shown in figure 10.24. If counting-up is generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes precedence. 3. Depending on the timing, TCNT may be incremented by a switch between different internal clock sources. When TCNT is internally clocked, an increment pulse is generated from the rising edge of an internal clock signal, that is, the divided system clock (). Therefore, as shown in figure 10.25 the switch is from a low clock signal to a high clock signal, the switchover is seen as a rising edge, causing TCNT to increment. 4. If timer W enters module standby mode while an interrupt request is generated, the interrupt request cannot be cleared. Before entering module standby mode, disable interrupt requests.
Rev. 3.00 May 15, 2007 Page 181 of 518 REJ09B0152-0300
Section 10 Timer W
5. When an input capture function is specified, inputting a valid edge to the FTIOA to FTIOD pins sets the status bit of the corresponding TSRW, even if the CTS bit in TMRW is 0 (counting disabled state). When the relevant interrupt is enabled, this inputting generates an interrupt. 6. When the input capture timing conflicts with the corresponding GRA to GRD write timing, a. the written values are reflected in GRA to GRD. b. the status flag of the corresponding TSRW is set. 7. When the input capture timing conflicts with the GRA to GRD read timing, the read values are ones before capturing. The captured values can be read one clock after the capturing. 8. When the input capture A or B conflicts with the GRC or GRD write timing as the input capture operation in buffer mode, a. the captured values are reflected in GRA or GRB. b. the written values are reflected in GRC or GRD. (The values in GRC or GRD are not ones in GRA or GRB before capturing.) 9. When the compare match timing conflicts with the GRA to GRD write timing as the compare match operation, a. the written values are reflected in GRA to GRD. b. the FTIOA to FTIOD output changes by the compare match. 10. When the compare match A or B conflicts with the GRA or GRB write timing as the compare match operation in buffer mode, a. the written values are reflected in GRA or GRB. (The values in GRA or GRB are not ones in GRC or GRD of the buffer register.) b. the FTIOA or FTIOB output changes by the compare match. 11. When the compare match A or B conflicts with the GRC or GRD write timing as the compare match operation in buffer mode, a. the values in GRA or GRB are ones in GRC or GRD before writing. b. the FTIOA or FTIOB output changes by the compare match. 12. When GRC or GRD is specified to the compare match output as the compare match operation in buffer mode, FTIOC or FTIOD output changes by the GRC or GRD compare match. 13. When w, w/4, w/16, or FTCI input is selected as the count clock, counting is enabled even in subactive and subsleep modes. Counting is disabled during the oscillation stabilization time in transition to the active mode. 14. When w, w/4, w/16, or FTCI input is selected as the count clock, counting is enabled in active and sleep modes although counting may be misaligned by one in transition from the active to subactive mode.
Rev. 3.00 May 15, 2007 Page 182 of 516 REJ09B0152-0300
Section 10 Timer W
TCNT write cycle T2 T1
Address
TCNT address
Write signal Counter clear signal TCNT
N
H'0000
Figure 10.24 Contention between TCNT Write and Clear
Previous clock New clock
Count clock
TCNT
N
N+1
N+2
N+3
The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count.
Figure 10.25 Internal Clock Switching and TCNT Operation
Rev. 3.00 May 15, 2007 Page 183 of 518 REJ09B0152-0300
Section 10 Timer W
Rev. 3.00 May 15, 2007 Page 184 of 516 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
Section 11 Realtime Clock (RTC)
The realtime clock (RTC) is a timer used to count time ranging from a second to a week. Interrupts can be generated ranging from 0.25 seconds to a week. Figure 11.1 shows the block diagram of the RTC.
11.1
* * * * * * * *
Features
Counts seconds, minutes, hours, and day-of-week Start/stop function Reset function Readable/writable counter of seconds, minutes, hours, and day-of-week with BCD codes Periodic (0.25 seconds, 0.5 seconds, one second, minute, hour, day, and week) interrupts 8-bit free running counter Selection of clock source Use of module standby mode enables this module to be placed in standby mode independently when not used. (The RTC is operating as the initial value. For details, refer to section 5.4, Module Standby Function.)
RTC3000A_000120030300
Rev. 3.00 May 15, 2007 Page 185 of 516 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
PSS 32-kHz oscillator circuit
RTCCSR
1/4
RSECDR
RMINDR
Internal data bus
RHRDR TMOW Clock count control circuit
RWKDR
RTCCR1
RTCCR2
RTCFLG
Interrupt control circuit [Legend] RTCCSR: RSECDR: RMINDR: RHRDR: RWKDR: RTCCR1: RTCCR2: RTCFLG: PSS: Clock source select register Second date register/free running counter data register Minute date register Hour date register Day-of-week date register RTC control register 1 RTC control register 2 RTC interrupt flag register Prescaler S
Interrupt
Figure 11.1 Block Diagram of RTC
11.2
Input/Output Pin
Table 11.1 shows the pin configuration of the RTC. Table 11.1 Pin Configuration
Name Clock output Abbreviation I/O TMOW Output Function RTC divided clock output
Rev. 3.00 May 15, 2007 Page 186 of 516 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.3
Register Descriptions
The RTC has the following registers. * * * * * * * * Second data register/free running counter data register (RSECDR) Minute data register (RMINDR) Hour data register (RHRDR) Day-of-week data register (RWKDR) RTC control register 1 (RTCCR1) RTC control register 2 (RTCCR2) Clock source select register (RTCCSR) RTC interrupt flag register (RTCFLG) Second Data Register/Free Running Counter Data Register (RSECDR)
11.3.1
RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit read register used as a counter, when it operates as a free running counter. For more information on reading seconds, minutes, hours, and day-of-week, see section 11.4.3, Data Reading Procedure.
Bit 7 Bit Name BSY Initial Value --/(0)* R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 Note: * SC12 SC11 SC10 SC03 SC02 SC01 SC00 --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* R/W R/W R/W R/W R/W R/W R/W Counting One's Position of Seconds Counts on 0 to 9 once per second. When a carry is generated, 1 is added to the ten's position. Counting Ten's Position of Seconds Counts on 0 to 5 for 60-second counting.
Initial value after a reset caused by the RST bit in RTCCR1.
Rev. 3.00 May 15, 2007 Page 187 of 518 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.3.2
Minute Data Register (RMINDR)
RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59.
Bit 7 Bit Name BSY Initial Value --/(0)* R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 Note: * MN12 MN11 MN10 MN03 MN02 MN01 MN00 --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* R/W R/W R/W R/W R/W R/W R/W Counting One's Position of Minutes Counts on 0 to 9 once per minute. When a carry is generated, 1 is added to the ten's position. Counting Ten's Position of Minutes Counts on 0 to 5 for 60-minute counting.
Initial value after a reset caused by the RST bit in RTCCR1.
Rev. 3.00 May 15, 2007 Page 188 of 516 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.3.3
Hour Data Register (RHRDR)
RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in RTCCR1.
Bit 7 Bit Name BSY Initial Value --/(0)* R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 5 4 3 2 1 0 Note: * -- HR11 HR10 HR03 HR02 HR01 HR00 0 --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* --/(0)* -- R/W R/W R/W R/W R/W R/W Reserved This bit is always read as 0. Counting Ten's Position of Hours Counts on 0 to 2 for ten's position of hours. Counting One's Position of Hours Counts on 0 to 9 once per hour. When a carry is generated, 1 is added to the ten's position.
Initial value after a reset caused by the RST bit in RTCCR1.
Rev. 3.00 May 15, 2007 Page 189 of 518 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.3.4
Day-of-Week Data Register (RWKDR)
RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0.
Bit 7 Bit Name BSY Initial Value --/(0)* R/W R Description RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers. When this bit is 0, the values of second, minute, hour, and day-of-week data registers must be adopted. 6 to 3 2 1 0 -- WK2 WK1 WK0 All 0 --/(0)* --/(0)* --/(0)* -- R/W R/W R/W Reserved These bits are always read as 0. Day-of-Week Counting Day-of-week is indicated with a binary code 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday 111: Reserved (setting prohibited) Note: * Initial value after a reset caused by the RST bit in RTCCR1.
Rev. 3.00 May 15, 2007 Page 190 of 516 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.3.5
RTC Control Register 1 (RTCCR1)
RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 11.2.
Bit 7 Bit Name RUN Initial Value --/(0)* R/W R/W Description RTC Operation Start 0: Stops RTC operation 1: Starts RTC operation Operating Mode 0: RTC operates in 12-hour mode. RHRDR counts on 0 to 11. 1: RTC operates in 24-hour mode. RHRDR counts on 0 to 23. A.M./P.M. 0: Indicates a.m. when RTC is in the 12-hour mode. 1: Indicates p.m. when RTC is in the 12-hour mode. Reset 0: Normal operation 1: Resets registers and control circuits except RTCCSR and this bit. Clear this bit to 0 after having been set to 1. Interrupt Occurrence Timing 0: Periodic interrupts of second, minute, hour, and day-ofweek occur during the RTC busy period. 1: Periodic interrupts of second, minute, hour, and day-ofweek occur immediately after the RTC busy period finishes. Reserved These bits are always read as 0.
6
12/24
--/(0)*
R/W
5
PM
--/(0)*
R/W
4
RST
0
R/W
3
INT
--/(0)*
R/W
2 to 0 Note: *
--
All 0
--
Initial value after a reset caused by the RST bit in RTCCR1.
Noon 24-hour count 12-hour count PM 0 0 12345678 12345678 0 (Morning) 9 10 11 12 13 14 15 16 17 9 10 11 0 1 2 3 4 5 1 (Afternoon)
24-hour count 18 19 20 21 22 23 0 12-hour count 6 7 8 9 10 11 0 1 (Afternoon) 0 PM
Figure 11.2 Definition of Time Expression
Rev. 3.00 May 15, 2007 Page 191 of 518 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.3.6
RTC Control Register 2 (RTCCR2)
RTCCR2 controls RTC periodic interrupts of week, day, hour, minute, one second, 0.5 seconds, and 0.25 seconds. Enabling interrupts of week, day, hour, minute, one second, 0.5 seconds, and 0.25 seconds sets the corresponding flag to 1 in the RTC interrupt flag register (RTCFLG) when an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC operates as a free running counter.
Bit 7 Bit Name FOIE Initial Value --/(0)* R/W R/W Description Free Running Counter Overflow Interrupt Enable 0: Disables an overflow interrupt 1: Enables an overflow interrupt 6 WKIE --/(0)* R/W Week Periodic Interrupt Enable 0: Disables a week periodic interrupt 1: Enables a week periodic interrupt 5 DYIE --/(0)* R/W Day Periodic Interrupt Enable 0: Disables a day periodic interrupt 1: Enables a day periodic interrupt 4 HRIE --/(0)* R/W Hour Periodic Interrupt Enable 0: Disables an hour periodic interrupt 1: Enables an hour periodic interrupt 3 MNIE --/(0)* R/W Minute Periodic Interrupt Enable 0: Disables a minute periodic interrupt 1: Enables a minute periodic interrupt 2 1SEIE --/(0)* R/W One-Second Periodic Interrupt Enable 0: Disables a one-second periodic interrupt 1: Enables a one-second periodic interrupt 1 05SEIE --/(0)* R/W 0.5-Second Periodic Interrupt Enable 0: Disables a 0.5-second periodic interrupt 1: Enables a 0.5-second periodic interrupt 0 025SEIE --/(0)* R/W 0.25-Second Periodic Interrupt Enable 0: Disables a 0.25-second periodic interrupt 1: Enables a 0.25-second periodic interrupt Note: * Initial value after a reset caused by the RST bit in RTCCR1.
Rev. 3.00 May 15, 2007 Page 192 of 516 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.3.7
Clock Source Select Register (RTCCSR)
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than W/4 is selected, the RTC is disabled and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter, RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to the FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock generated by dividing the system clock by 32, 16, 8, or 4 is output in active or sleep mode. W is output in active, sleep, subactive, subsleep, or watch mode.
Bit 7 6 5 4 Bit Name -- RCS6 RCS5 SUB32K Initial Value 0 0 0 0 R/W -- R/W R/W R/W Description Reserved This bit is always read as 0. Clock Output Selection Select a clock output from the TMOW pin when enabling TMOW output in PMR1. 000: /4 010: /8 100: /16 110: /32 xx1: W 3 2 1 0 RCS3 RCS2 RCS1 RCS0 1 0 0 0 R/W R/W R/W R/W Clock Source Selection 0000: /8 Free running counter operation 0001: /32 Free running counter operation 0010: /128 Free running counter operation 0011: /256 Free running counter operation 0100: /512 Free running counter operation 0101: /2048 Free running counter operation 0110: /4096 Free running counter operation 0111: /8192 Free running counter operation 1000: W/4 RTC operation 1001 to 1111: Setting prohibited
Rev. 3.00 May 15, 2007 Page 193 of 518 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.3.8
RTC Interrupt Flag Register (RTCFLG)
RTCFLG sets the corresponding flag when an interrupt occurs. Each flag is not cleared automatically even if the interrupt is accepted. To clear the flag, 0 should be written to the flag.
Bit 7 Bit Name FOIFG Initial Value --/(0)*
1
R/W
2
Description
R/(W)* [Setting condition] When a free running counter overflows [Clearing condition] 0 is written to FOIFG when FOIFG = 1
6
WKIFG
--/(0)*1
R/(W)*2 [Setting condition] When a week periodic interrupt occurs [Clearing condition] 0 is written to WKIFG when WKIFG = 1
5
DYIFG
--/(0)*
1
R/(W)* [Setting condition] When a day periodic interrupt occurs [Clearing condition] 0 is written to DYIFG when DYIFG = 1
2
4
HRIFG
--/(0)*
1
R/(W)* [Setting condition] When an hour periodic interrupt occurs [Clearing condition] 0 is written to HRIFG when HRIFG = 1
2
3
MNIFG
--/(0)*
1
R/(W)* [Setting condition] When a minute periodic interrupt occurs [Clearing condition] 0 is written to MNIFG when MNIFG = 1
2
2
1SEIFG
--/(0)*
1
R/(W)* [Setting condition] When a one-second periodic interrupt occurs [Clearing condition] 0 is written to 1SEIFG when 1SEIFG = 1
2
Rev. 3.00 May 15, 2007 Page 194 of 516 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
Bit 1
Bit Name 05SEIFG
Initial Value --/(0)*
1
R/W
2
Description
R/(W)* [Setting condition] When a 0.5-second periodic interrupt occurs [Clearing condition] 0 is written to 05SEIFG when 05SEIFG = 1
0
025SEIFG --/(0)*
1
R/(W)* [Setting condition] When a 0.25-second periodic interrupt occurs [Clearing condition] 0 is written to 025SEIFG when 025SEIFG = 1
2
Notes: 1. Initial value after a reset caused by the RST bit in RTCCR1. 2. Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 195 of 518 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.4
11.4.1
Operation
Initial Settings of Registers after Power-On
The RTC registers that store second, minute, hour, and day-of-week data, control registers, and interrupt registers are not reset by a RES input, or by a reset source caused by a watchdog timer. Therefore, all registers must be set to their initial values after power-on. Once the register setting are made, the RTC provides an accurate time as long as power is supplied regardless of a RES input. 11.4.2 Initial Setting Procedure
Figure 11.3 shows the procedure for the initial setting of the RTC. To set the RTC again, also follow this procedure.
RUN in RTCCR1 = 0 RST in RTCCR1 = 1 RST in RTCCR1 = 0 Set RTCCSR, RSECDR, RMINDR, RHRDR, RWKDR, 12/24 in RTCCR1, and PM RUN in RTCCR1 = 1
RTC operation is stopped. RTC registers and clock count controller are reset.
Clock output and clock source are selected and second, minute, hour, day-of-week, operating mode, and a.m/p.m are set. RTC operation is started.
Figure 11.3 Initial Setting Procedure
Rev. 3.00 May 15, 2007 Page 196 of 516 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.4.3
Data Reading Procedure
When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 11.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1. Check the setting of the BSY bit, and when the BSY bit changes from 1 to 0, read from the second, minute, hour, and day-of-week registers. When about 62.5 ms is passed after the BSY bit is set to 1, the registers are updated, and the BSY bit is cleared to 0. 2. When INT in RTCCR1 is cleared to 0 and an interrupt is used, read from the second, minute, hour, and day-of-week registers after the relevant flag in RTCFLG is set to 1 and the BSY bit is confirmed to be 0. When INT in RTCCR1 is set to 1 and an interrupt is used, read from the second, minute, hour, and day-of-week registers after the relevant flag in RTCFLG is set to 1. 3. Read from the second, minute, hour, and day-of-week registers twice in a row, and if there is no change in the read data, the read data is used.
Before update BSY bit = 0 RWKDR = H'03, RHDDR = H'13, RMINDR = H'46, RSECDR = H'59
Processing flow
(1) Day-of-week data register read (2) Hour data register read (3) Minute data register read
H'03 H'13 H'46
BSY bit -> 1 (under data update) After update BSY bit -> 0 RWKDR = H'03, RHDDR = H'13, RMINDR = H'47, RSECDR = H'00
(4) Second data register read
H'00
Figure 11.4 Example: Reading of Inaccurate Time Data
Rev. 3.00 May 15, 2007 Page 197 of 518 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.5
Interrupt Sources
There are eight kinds of RTC interrupts: a free-running counter overflow, week interrupt, day interrupt, hour interrupt, minute interrupt, one-second interrupt, 0.5-second interrupt, and 0.25second interrupt. When using an interrupt, set the IENRTC (RTC interrupt request enable) bit in IENR1 to 1 last after other registers are set. When an interrupt request of the RTC occurs, the corresponding flag in RTCFLG is set to 1. When clearing the flag, write 0. Table 11.2 Interrupt Sources
Interrupt Name Overflow interrupt Week periodic interrupt Day periodic interrupt Hour periodic interrupt Minute periodic interrupt One-second periodic interrupt 0.5-second periodic interrupt 0.25-second periodic interrupt Interrupt Source Occurs when the free running counter is overflowed. Interrupt Enable Bit FOIE
Occurs every week when the day-of-week date WKIE register value becomes 0. Occurs every day when the day-of-week date register is counted. DYIE
Occurs every hour when the hour date register HRIE is counted. Occurs every minute when the minute date register is counted. Occurs every second when the one-second date register is counted. Occurs every 0.5 seconds. Occurs every 0.25 seconds. MNIE 1SEIE 05SEIE 025SEIE
Rev. 3.00 May 15, 2007 Page 198 of 516 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
11.6
11.6.1
Usage Notes
Note on Clock Count
The subclock must be connected to the 32.768-kHz resonator. When the 38.4-kHz resonator etc. is connected, the correct time count is not possible. 11.6.2 Note when Using RTC Interrupts
The RTC registers are not reset by a RES input, power-on, or overflow of the watchdog timer, and their values are undefined after power-on. When using RTC interrupts, make sure to initialize the values before setting the IENRTC bit in IENR1 to 1.
Rev. 3.00 May 15, 2007 Page 199 of 518 REJ09B0152-0300
Section 11 Realtime Clock (RTC)
Rev. 3.00 May 15, 2007 Page 200 of 516 REJ09B0152-0300
Section 12 Watchdog Timer
Section 12 Watchdog Timer
This LSI incorporates the watchdog timer (WDT). The WDT is an 8-bit timer that can generate an internal reset signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog timer function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows.
12.1
Features
The WDT features are described below. * Selectable from eleven counter input clocks Ten internal clock sources (/64, /128, /256, /512, /1024, /2048, /4096, /8192, W/16, and W/256) or the on-chip oscillator (ROSC/2048) can be selected as the timer-counter clock. * Watchdog timer mode If the counter overflows, this LSI is internally reset. * Interval timer mode If the counter overflows, an interval timer interrupt is generated. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (The WDT is operating as the initial value. For details, refer to section 5.4, Module Standby Function.)
WDT0110A_000020020200
Rev. 3.00 May 15, 2007 Page 201 of 516 REJ09B0152-0300
Section 12 Watchdog Timer
Figure 12.1 shows a block diagram of the WDT.
TMWD
PSS
TCWD
[w/16 or w/256]
TCSRWD2
Internal data bus
Interrupt/reset control Internal reset signal or interrupt request signal
On-chip oscillator
ROSC
TCSRWD1
[Legend] TCSRWD1: TCSRWD2: TCWD: TMWD: PSS: Timer control/status register WD1 Timer control/status register WD2 Timer counter WD Timer mode register WD Prescaler S
Figure 12.1 Block Diagram of Watchdog Timer
12.2
Register Descriptions
The watchdog timer has the following registers. * * * * Timer control/status register WD1 (TCSRWD1) Timer control/status register WD2 (TCSRWD2) Timer counter WD (TCWD) Timer mode register WD (TMWD)
Rev. 3.00 May 15, 2007 Page 202 of 516 REJ09B0152-0300
Section 12 Watchdog Timer
12.2.1
Timer Control/Status Register WD1 (TCSRWD1)
TCSRWD1 performs the TCSRWD1 and TCWD write control. TCSRWD1 also controls the watchdog timer operation and indicates the operating state. TCSRWD1 must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit 7 Bit Name B6WI Initial Value 1 R/W R/W Description Bit 6 Write Inhibit The TCWE bit can be written only when the write value of the B6WI bit is 0. This bit is always read as 1. 6 TCWE 0 R/W Timer Counter WD Write Enable TCWD can be written when the TCWE bit is set to 1. When writing data to this bit, the write value for bit 7 must be 0. 5 B4WI 1 R/W Bit 4 Write Inhibit The TCSRWE bit can be written only when the write value of the B4WI bit is 0. This bit is always read as 1. 4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the write value for bit 5 must be 0. 3 B2WI 1 R/W Bit 2 Write Inhibit The WDON bit can be written only when the write value of the B2WI bit is 0. This bit is always read as 1.
Rev. 3.00 May 15, 2007 Page 203 of 518 REJ09B0152-0300
Section 12 Watchdog Timer
Bit 2
Bit Name WDON
Initial Value 1
R/W R/W
Description Watchdog Timer On TCWD starts counting up when the WDON bit is set to 1 and halts when the WDON bit is cleared to 0. [Setting condition] * * * When 1 is written to the WDON bit and 0 to the B2WI bit while the TCSRWE bit is 1 Reset by RES pin When 0 is written to the WDON bit and 0 to the B2WI bit while the TCSRWE bit is 1
[Clearing conditions]
1
B0WI
1
R/W
Bit 0 Write Inhibit The WRST bit can be written only when the write value of the B0WI bit is 0. This bit is always read as 1.
0
WRST
0
R/W
Watchdog Timer Reset Indicates whether a reset caused by the watchdog timer is generated. This bit is not cleared by a reset caused by the watchdog timer. [Setting condition] When TCWD overflows and an internal reset signal is generated [Clearing conditions] * * Reset by RES pin When 0 is written to the WRST bit and 0 to the B0WI bit while the TCSRWE bit is 1
Rev. 3.00 May 15, 2007 Page 204 of 516 REJ09B0152-0300
Section 12 Watchdog Timer
12.2.2
Timer Control/Status Register WD2 (TCSRWD2)
TCSRWD2 performs the TCSRWD2 write control, mode switching, and interrupt control. TCSRWD2 must be rewritten by using the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit 7 Bit Name OVF Initial Value 0 R/W
1
Description
R/(W)* Overflow Flag Indicates that TCWD has overflowed (changes from H'FF to H'00). [Setting condition] When TCWD overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, this bit is cleared automatically by the internal reset after it has been set. [Clearing condition] * When TCSRWD2 is read when OVF = 1, then 0 is written to OVF
6
B5WI
1
R/(W)*2 Bit 5 Write Inhibit The WT/IT bit can be written only when the write value of the B5WI bit is 0. This bit is always read as 1.
5
WT/IT
0
R/(W)*3 Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Watchdog timer mode 1: Interval timer mode
4
B3WI
1
R/(W)* Bit 3 Write Inhibit The IEOVF bit can be written only when the write value of the B3WI bit is 0. This bit is always read as 1.
2
3
IEOVF
0
R/(W)*3 Overflow Interrupt Enable Enables or disables an overflow interrupt request in interval timer mode. 0: Disables an overflow interrupt 1: Enables an overflow interrupt
Rev. 3.00 May 15, 2007 Page 205 of 518 REJ09B0152-0300
Section 12 Watchdog Timer
Bit 2 to 0
Bit Name
Initial Value All 1
R/W
Description Reserved These bits are always read as 1.
Notes: 1. Only 0 can be written to clear the flag. 2. Write operation is necessary because this bit controls data writing to other bit. This bit is always read as 1. 3. Writing is possible only when the write conditions are satisfied.
12.2.3
Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD1 is set to 1. TCWD is initialized to H'00.
Rev. 3.00 May 15, 2007 Page 206 of 516 REJ09B0152-0300
Section 12 Watchdog Timer
12.2.4
Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit 7 to 4 3 2 1 0 Bit Name CKS3 CKS2 CKS1 CKS0 Initial Value All 1 0 0 0 0 R/W R/W R/W R/W R/W Description Reserved These bits are always read as 1. Clock Select 3 to 0 Select the clock to be input to TCWD. 00xx: On-chip oscillator: counts on ROSC/2048 0100: Internal clock: counts on W/16 0101: Internal clock: counts on W/256 011x: Reserved 1000: Internal clock: counts on /64 1001: Internal clock: counts on /128 1010: Internal clock: counts on /256 1011: Internal clock: counts on /512 1100: Internal clock: counts on /1024 1101: Internal clock: counts on /2048 1110: Internal clock: counts on /4096 1111: Internal clock: counts on 8192 For the on-chip oscillator overflow periods, see section 21, Electrical Characteristics. In active (medium-speed), sleep (medium-speed), subactive, and subsleep modes, the 00xx value and the interval timer mode cannot be set simultaneously. In subactive and subsleep modes, when the subclock frequency is W/8, the 010x value and the interval timer mode cannot be set simultaneously. [Legend] x: Don't care.
Rev. 3.00 May 15, 2007 Page 207 of 518 REJ09B0152-0300
Section 12 Watchdog Timer
12.3
12.3.1
Operation
Watchdog Timer Mode
The watchdog timer is provided with an 8-bit up-counter. To use it as the watchdog timer, clear the WT/IT bit in TCSRWD2 to 0. (To write the WT/IT bit, two write accesses are required.) If 1 is written to the WDON bit and 0 to the B2WI bit simultaneously when the TCSRWE bit in TCSRWD1 is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD1 are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 512 clock cycles by the on-chip oscillator (ROSC). TCWD is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the TCWD set value. Figure 12.2 shows an example of watchdog timer operation.
Example: With 30-ms overflow period when = 4 MHz 4 x 106 8192 x 30 x 10-3 = 14.6
Therefore, 256 - 15 = 241 (H'F1) is set in TCWD. TCWD overflow
H'FF H'F1 TCWD count value
H'00 Start H'F1 written to TCWD Internal reset signal 512 clock cycles by Rosc H'F1 written to TCWD Reset generated
Figure 12.2 Example of Watchdog Timer Operation
Rev. 3.00 May 15, 2007 Page 208 of 516 REJ09B0152-0300
Section 12 Watchdog Timer
12.3.2
Interval Timer Mode
Figure 12.3 shows the operation in interval timer mode. To use the WDT as an interval timer, set the WT/IT bit in TCSRWD2 to 1. When the WDT is used as an interval timer, an interval timer interrupt request is generated each time the TCWD overflows. Therefore, an interval timer interrupt can be generated at intervals.
H'FF
TCWD count value Time H'00 WT/IT = 1 Interval timer Interval timer Interval timer Interval timer Interval timer interrupt interrupt interrupt interrupt interrupt request generated request generated request generated request generated request generated
Figure 12.3 Interval Timer Mode Operation 12.3.3 Timing of Overflow Flag (OVF) Setting
Figure 12.4 shows the timing of the OVF flag setting. The OVF flag in TCSRWD2 is set to 1 if TCWD overflows. At the same time, a reset signal is output in watchdog timer mode and an interval timer interrupt is generated in interval timer mode.
TCWD H'FF H'00
Overflow signal
OVF
Figure 12.4 Timing of OVF Flag Setting
Rev. 3.00 May 15, 2007 Page 209 of 518 REJ09B0152-0300
Section 12 Watchdog Timer
12.4
Interrupt
During interval timer mode operation, an overflow generates an interval timer interrupt. The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSRWD2. The OVF flag must be cleared to 0 in the interrupt handling routine.
12.5
12.5.1
Usage Notes
Switching between Watchdog Timer Mode and Interval Timer Mode
If modes are switched between watchdog timer and interval timer, while the WDT is operating, an error may occur in the count value. Software must stop the watchdog timer (by clearing the WDON bit to 0) before switching modes. 12.5.2 Module Standby Mode Control
The WDCKSTP bit in CKSTPR2 is valid when the WDON bit in the timer control/status register WD1 (TCSRWD1) is cleared to 0. The WDCKSTP bit can be cleared to 0 while the WDON bit is set to 1 (while the watchdog timer is operating). However, the watchdog timer does not enter module standby mode but continues operating. When the WDON bit is cleared to 0 by software after the watchdog timer stops operating, the WDCKSTP bit is valid at the same time and the watchdog timer enters module standby mode. 12.5.3 Clearing the WT/IT or IEOVF Bit in TCSRWD2 to 0
When clearing the WT/IT or IEOVF bit in the timer control/status register WD2 (TCSRWD2) to 0, the corresponding bit may not be cleared to 0 depending on the program address. In particular, if lower two bits in the address of the MOV.B instruction to transfer a value to TCSRWD2 are B'10, the WT/IT or IEOVF bit is successfully cleared to 0, whereas if lower two bits in the address are B'00, the WT/IT or IEOVF bit may not be cleared to 0. To avoid this failure, make sure to use the assembly program shown in table 12.1, when clearing the WT/IT or IEOVF bit to 0. Specify TCSRWD2 by the 8-bit absolute address, and LABEL by the 16-bit absolute address. Don't change nor add instructions. The value of "xx" in line 1 and line 4 must be set according to table 12.2. Use an arbitrary 8-bit general register for Rn and Rm. In addition, Address1 in table 12.1 shows an example when the WT/IT or IEOVF bit is cleared to 0 successfully by the MOV.B instruction in line 2. Address2 in table 12.1 shows an example when the WT/IT or IEOVF bit fails to be cleared to 0 by the MOV.B instruction in line 2, but cleared to 0 by the MOV.B instruction in line 6.
Rev. 3.00 May 15, 2007 Page 210 of 516 REJ09B0152-0300
Section 12 Watchdog Timer
Table 12.1 Assembly Program for Clearing WT/IT or IEOVF Bit to 0
Address1 Address2 Assembly Program H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AC H'00AE H'0232 H'0234 H'0236 H'0238 H'023A H'023E H'0240 MOV.B #H'xx,Rn MOV.B Rn,@TCSRWD2:8 ; Clear success in case of Address1 and failure in case of Address2 MOV.B @TCSRWD2:8,Rm ; TCSRWD2 read AND.B #H'xx,Rm BEQ LABEL:16 ; Judgment of clear ; Jumps to LABEL if it is a clear success
MOV.B Rn,@TCSRWD2:8 ; Clear success in case of Address2 LABEL NOP
Table 12.2 The Value of "xx"
Bit(s) Cleared to 0 Both WT/IT and IEOVF Only WT/IT Only IEOVF The Value of "xx" in Line 1 07 17 47 The Value of "xx" in Line 4 28 20 08
Rev. 3.00 May 15, 2007 Page 211 of 518 REJ09B0152-0300
Section 12 Watchdog Timer
Rev. 3.00 May 15, 2007 Page 212 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
Section 13 Asynchronous Event Counter (AEC)
The asynchronous event counter (AEC) is an event counter that is incremented by external event clock or internal clock input. Figure 13.1 shows a block diagram of the asynchronous event counter.
13.1
Features
* Can count asynchronous events Can count external events input asynchronously without regard to the operation of system clocks () or subclocks (SUB). * Can be used as two-channel independent 8-bit event counter or single-channel independent 16bit event counter. * Event/clock input is enabled when IRQAEC goes high or event counter PWM output (IECPWM) goes high. * Both rising and falling edge sensing can be used for IRQAEC or event counter PWM output (IECPWM) interrupts. When the asynchronous counter is not used, they can be used as independent interrupts. * When an event counter PWM is used, event clock input enabling/disabling can be controlled at a constant cycle. An event counter PWM can be output to the AECPWM pin. * Selection of four clock sources Three internal clocks (/2, /4, or /8) or external event can be selected. * Both rising and falling edge counting is possible for the AEVL and AEVH pins. * Counter resetting and halting of the count-up function can be controlled by software. * Automatic interrupt generation on detection of an event counter overflow * Use of module standby mode enables this module to be placed in standby mode independently when not used. (The asynchronous event counter is halted as the initial value. For details, refer to section 5.4, Module Standby Function.)
Rev. 3.00 May 15, 2007 Page 213 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
IRREC PSS ECCR ECCSR
/2 /4, /8 ECH (8 bits)
OVH
CK
AEVH
Edge sensing circuit
OVL
CK
AEVL IRQAEC AECPWM
Edge sensing circuit Edge sensing circuit
IECPWM
To CPU interrupt (IRREC2)
ECPWCR
w/16
PWM waveform generator /2, /4, /8, /16, /32, /64
ECPWDR
AEGSR
[Legend] ECPWCR: ECPWDR: AEGSR: ECCSR: Event counter PWM compare register Event counter PWM data register Input pin edge select register Event counter control/status register ECL: ECCR: ECH: PSS: Event counter L Event counter control register Event counter H Prescaler s
Figure 13.1 Block Diagram of Asynchronous Event Counter
Rev. 3.00 May 15, 2007 Page 214 of 516 REJ09B0152-0300
Internal data bus
ECL (8 bits)
Section 13 Asynchronous Event Counter (AEC)
13.2
Input/Output Pins
Table 13.1 shows the pin configuration of the asynchronous event counter. Table 13.1 Pin Configuration
Name Abbreviation I/O Input Input Input Output Function Event input pin for input to event counter H Event input pin for input to event counter L Input pin for interrupt enabling event input Event counter PWM output pin
Asynchronous event AEVH input H Asynchronous event AEVL input L Event input enable interrupt input IRQAEC
Event counter PWM AECPWM output
13.3
Register Descriptions
The asynchronous event counter has the following registers. * * * * * * * Event counter PWM compare register (ECPWCR) Event counter PWM data register (ECPWDR) Input pin edge select register (AEGSR) Event counter control register (ECCR) Event counter control/status register (ECCSR) Event counter H (ECH) Event counter L (ECL)
Rev. 3.00 May 15, 2007 Page 215 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.3.1
Event Counter PWM Compare Register (ECPWCR)
ECPWCR sets the one conversion period of the event counter PWM waveform.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name ECPWCR15 ECPWCR14 ECPWCR13 ECPWCR12 ECPWCR11 ECPWCR10 ECPWCR9 ECPWCR8 ECPWCR7 ECPWCR6 ECPWCR5 ECPWCR4 ECPWCR3 ECPWCR2 ECPWCR1 ECPWCR0 Initial Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description One Conversion Period of Event Counter PWM Waveform When the ECPWME bit in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR should not be modified. When changing the conversion period, the event counter PWM must be halted by clearing the ECPWME bit in AEGSR to 0 before modifying ECPWCR.
Rev. 3.00 May 15, 2007 Page 216 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.3.2
Event Counter PWM Data Register (ECPWDR)
ECPWDR controls data of the event counter PWM waveform generator.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name ECPWDR15 ECPWDR14 ECPWDR13 ECPWDR12 ECPWDR11 ECPWDR10 ECPWDR9 ECPWDR8 ECPWDR7 ECPWDR6 ECPWDR5 ECPWDR4 ECPWDR3 ECPWDR2 ECPWDR1 ECPWDR0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W W W W W W W W W W W W W W W W W Description Data Control of Event Counter PWM Waveform Generator When the ECPWME bit in AEGSR is 1, the event counter PWM is operating and therefore ECPWDR should not be modified. When changing the conversion cycle, the event counter PWM must be halted by clearing the ECPWME bit in AEGSR to 0 before modifying ECPWDR. The read value is undefined.
Rev. 3.00 May 15, 2007 Page 217 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.3.3
Input Pin Edge Select Register (AEGSR)
AEGSR selects rising, falling, or both edge sensing for the AEVH, AEVL, and IRQAEC pins, and controls IRQAEC/IECPWM.
Bit 7 6 Bit Name AHEGS1 AHEGS0 Initial Value 0 0 R/W R/W R/W Description AEC Edge Select H Select rising, falling, or both edge sensing for the AEVH pin. 00: Falling edge on AEVH pin is sensed 01: Rising edge on AEVH pin is sensed 10: Both edges on AEVH pin are sensed 11: Setting prohibited 5 4 ALEGS1 ALEGS0 0 0 R/W R/W AEC Edge Select L Select rising, falling, or both edge sensing for the AEVL pin. 00: Falling edge on AEVL pin is sensed 01: Rising edge on AEVL pin is sensed 10: Both edges on AEVL pin are sensed 11: Setting prohibited 3 2 AIEGS1 AIEGS0 0 0 R/W R/W IRQAEC Edge Select Select rising, falling, or both edge sensing for the IRQAEC pin. 00: Falling edge on IRQAEC pin is sensed 01: Rising edge on IRQAEC pin is sensed 10: Both edges on IRQAEC pin are sensed 11: Setting prohibited 1 ECPWME 0 R/W Event Counter PWM Enable Controls operation of event counter PWM and selection of IRQAEC. 0: AEC PWM halted, IRQAEC selected 1: AEC PWM enabled, IRQAEC not selected 0 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to.
Rev. 3.00 May 15, 2007 Page 218 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.3.4
Event Counter Control Register (ECCR)
ECCR controls the counter input clock and PWM clock.
Bit 7 6 Bit Name ACKH1 ACKH0 Initial Value 0 0 R/W R/W R/W Description AEC Clock Select H Select the clock used by ECH. 00: AEVH pin input 01: /2 10: /4 11: /8 5 4 ACKL1 ACKL0 0 0 R/W R/W AEC Clock Select L Select the clock used by ECL. 00: AEVL pin input 01: /2 10: /4 11: /8 3 2 1 PWCK2 PWCK1 PWCK0 0 0 0 R/W R/W R/W Event Counter PWM Clock Select Select the event counter PWM clock. 000: /2 001: /4 010: /8 011: /16 100: /32 101: /64 110: W/16 111: Setting prohibited When changing the event counter PWM clock, the ECPWME bit in AEGSR must be cleared to 0 to stop the PWM before rewriting this setting. 0 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to.
Rev. 3.00 May 15, 2007 Page 219 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.3.5
Event Counter Control/Status Register (ECCSR)
ECCSR controls counter overflow detection, counter resetting, and count-up function.
Bit 7 Bit Name OVH Initial Value 0 R/W R/W* Description Counter Overflow H This is a status flag indicating that ECH has overflowed. [Setting condition] When ECH overflows from H'FF to H'00 [Clearing condition] When this bit is written to 0 after reading OVH = 1 6 OVL 0 R/W* Counter Overflow L This is a status flag indicating that ECL has overflowed. [Setting condition] When ECL overflows from H'FF to H'00 while CH2 is set to 1 [Clearing condition] When this bit is written to 0 after reading OVL = 1 5 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to. 4 CH2 0 R/W Channel Select Selects how ECH and ECL event counters are used 0: ECH and ECL are used together as a single-channel 16-bit event counter 1: ECH and ECL are used as two-channel 8-bit event counter 3 CUEH 0 R/W Count-Up Enable H Enables event clock input to ECH. 0: ECH event clock input is disabled (ECH value is retained) 1: ECH event clock input is enabled
Rev. 3.00 May 15, 2007 Page 220 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
Bit 2
Bit Name CUEL
Initial Value 0
R/W R/W
Description Count-Up Enable L Enables event clock input to ECL. 0: ECL event clock input is disabled (ECL value is retained) 1: ECL event clock input is enabled
1
CRCH
0
R/W
Counter Reset Control H Controls resetting of ECH. 0: ECH is reset 1: ECH reset is cleared and count-up function is enabled
0
CRCL
0
R/W
Counter Reset Control L Controls resetting of ECL. 0: ECL is reset 1: ECL reset is cleared and count-up function is enabled
Note:
*
Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 221 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.3.6
Event Counter H (ECH)
ECH is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECH also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL.
Bit 7 6 5 4 3 2 1 0 Bit Name ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVH pin, /2, /4, or /8, or the overflow signal from lower 8-bit counter ECL can be selected as the input clock source. ECH can be cleared to H'00 when the CRCH bit in ECCSR is cleared to 0.
13.3.7
Event Counter L (ECL)
ECL is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ECL also operates as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH.
Bit 7 6 5 4 3 2 1 0 Bit Name ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0 Initial Value 0 0 0 0 0 0 0 0 R/W R R R R R R R R Description Either the external asynchronous event AEVL pin, /2, /4, or /8 can be selected as the input clock source. ECL can be cleared to H'00 when the CRCL bit in ECCSR is cleared to 0.
Rev. 3.00 May 15, 2007 Page 222 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.4
13.4.1
Operation
16-Bit Counter Operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources--/2, /4, /8, or AEVL pin input--can be selected by means of bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0. Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 13.2 shows the software procedure when ECH and ECL are used as a 16-bit event counter.
Start
Clear CH2 to 0 Set ACKL1, ACKL0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 13.2 Software Procedure when Using ECH and ECL as 16-Bit Event Counter As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset, and as ACKL1 and ACKL0 are cleared to B00, the operating clock is asynchronous event input from the AEVL pin (using falling edge sensing). When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Rev. 3.00 May 15, 2007 Page 223 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.4.2
8-Bit Counter Operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. /2, /4, /8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and /2, /4, /8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR. Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and with bits ALEGS1 and ALEGS0 when AEVL pin input is selected. Note that the input clock is enabled when IRQAEC is high or IECPWM is high. When IRQAEC is low or IECPWM is low, the input clock is not input to the counter, which therefore does not operate. Figure 13.3 shows the software procedure when ECH and ECL are used as 8-bit event counters.
Start
Set CH2 to 1 Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1, AHEGS0, ALEGS1, and ALEGS0 Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0 Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 13.3 Software Procedure when Using ECH and ECL as 8-Bit Event Counters When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted. Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Rev. 3.00 May 15, 2007 Page 224 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.4.3
IRQAEC Operation
When the ECPWME bit in AEGSR is 0, the ECH and ECL input clocks are enabled when IRQAEC goes high. When IRQAEC goes low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually. IRQAEC can also operate as an interrupt source. Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated, interrupt request flag IRREC2 in IRR1 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIEGS1 and AIEGS0 in AEGSR. 13.4.4 Event Counter PWM Operation
When the ECPWME bit in AEGSR is 1, the ECH and ECL input clocks are enabled when event counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled cyclically by controlling event counter PWM. In this case, ECH and ECL cannot be controlled individually. IECPWM can also operate as an interrupt source. Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated, interrupt request flag IRREC2 in IRR1 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an interrupt request is sent to the CPU. Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits AIEGS1 and AIEGS0 in AEGSR.
Rev. 3.00 May 15, 2007 Page 225 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
Figure 13.4 and table 13.2 show examples of event counter PWM operation.
toff = T x (Ndr +1) ton: toff: Clock input enable time
ton tcm = T x (Ncm +1)
Clock input disable time tcm: One conversion period T: ECPWM input clock cycle Ndr: Value of ECPWDR Ncm: Value of ECPWCR
Figure 13.4 Event Counter Operation Waveform Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this condition, event counter PWM output (IECPWM) is fixed low. Table 13.2 Examples of Event Counter PWM Operation Conditions: fOSC = 4 MHz, f = 4 MHz, fW = 32.768 kHz, fW = 32.768 kHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11, ECPWDR value (Ndr) = H'16E3
Clock Source Selection /2 /4 /8 /16 /32 /64 W/16 Clock Source Cycle (T)* 0.5 s 1 s 2 s 4 s 8 s 16 s 488 s toff = T x (Ndr + 1) 2.93 ms 5.86 ms 11.72 ms 23.44 ms 46.88 ms 93.76 ms 2861.59 ms tcm = T x (Ncm ton = tcm - toff + 1) 15.625 ms 31.25 ms 62.5 ms 125.0 ms 250.0 ms 500.0 ms 15260.19 ms 12.695 ms 25.39 ms 50.78 ms 101.56 ms 203.12 ms 406.24 ms 12398.60 ms
ECPWCR Value (Ncm) H'7A11 D'31249
ECPWDR Value (Ndr) H'16E3 D'5859
Note:
*
toff minimum width
Rev. 3.00 May 15, 2007 Page 226 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.4.5
Operation of Clock Input Enable/Disable Function
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in AEGSR is 0, and by the event counter PWM output, IECPWM when ECPWME in AEGSR is 1. As this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending on the IRQAEC or IECPWM timing. Figure 13.5 shows an example of the operation.
Input event
IRQAEC or IECPWM Actually counted clock source
Edge generated by clock return
Counter value
N
N+1
N+2 Clock stopped
N+3
N+4
N+5
N+6
Figure 13.5 Example of Clock Control Operation
Rev. 3.00 May 15, 2007 Page 227 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.5
Operating States of Asynchronous Event Counter
The operating states of the asynchronous event counter are shown in table 13.3. Table 13.3 Operating States of Asynchronous Event Counter
Active Sleep Oscillation Stabilization Time Standby Clock Counter Source Highspeed Medium -speed HighMediumWatch Subactive Subsleep Standby to Active Subsleep Watch to Active to Active Remarks
speed speed
ECH, ECL
AEVH, AEVL

*
1
/2, /4, /8 PWM w/16
x
x
x
x
x
x
x

x
x
x
x x
x x
x
x
*
2
/2, /4, /8, /16, /32, /64
: Counting enabled x: Counting disabled (Counter value retained) Notes: 1. The count-up function is enabled only when IRQAEC/IECPWM = 1. 2. Output is in the high-impedance state during standby mode or the oscillation stabilization time from standby mode. [Legend]
Rev. 3.00 May 15, 2007 Page 228 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
13.6
Usage Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in 8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the counter. The correct value will not be returned if the event counter increments while being read. 2. For input to the AEVH and AEVL pins, use a clock with a frequency of up to 4.2 MHz within the range from 1.8 to 3.6 V and up to 10 MHz within the range from 2.7 to 3.6 V. For the high and low widths of the clock, see section 21, Electrical Characteristics. The duty cycle is arbitrary. Table 13.4 Maximum Clock Frequency
Mode Active (high-speed), sleep (high-speed) Active (medium-speed), sleep (medium-speed) fOSC = 4 MHz to 10 MHz (2.7 to 3.6 V) fOSC = 2 MHz to 4.2 MHz (1.8 to 3.6 V) Watch, subactive, subsleep, standby Maximum Clock Frequency Input to AEVH/AEVL Pin 4 to 10 MHz (2.7 to 3.6 V) 2 to 4.2 MHz (1.8 to 3.6 V) (OSC/8) 2 * fOSC (OSC/16) fOSC (OSC/32) 1/2 * fOSC (OSC/64) 1/4 * fOSC (W) (W/2) (W/4) W = 32.768 kHz or 38.4 kHz (W/8) 2000 kHz 1000 kHz 500 kHz 250 kHz
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1 second, or set both CUEH and CRCH to 1 at same time before clock input. When AEC is operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up. 4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore ECPWCR and ECPWDR should not be modified. When changing the data, clear the ECPWME bit in AEGSR to 0 (halt the event counter PWM) before modifying these registers. 5. The event counter PWM data register and event counter PWM compare register must be set so that event counter PWM data register < event counter PWM compare register. If the settings do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
Rev. 3.00 May 15, 2007 Page 229 of 516 REJ09B0152-0300
Section 13 Asynchronous Event Counter (AEC)
6. As synchronization is established internally when an IRQAEC interrupt is generated, a maximum error of 1 tcyc or 1tsubcyc will occur between clock halting and interrupt acceptance. 7. When pins in port 1 are used for AEC input/output, the PFCR and PMR1 registers should be set in the following order. a. Set the PFCR register. b. Set bits 4 to 0 after bit 5 (IRQAEC bit) in the PMR1 register has been cleared to 0. c. Set bit 5 (IRQAEC bit) in the PMR1 register to 1. At this time, bits 4 to 0 should not be changed and remain the same.
Rev. 3.00 May 15, 2007 Page 230 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
The serial communication interface 3 (SCI3) can handle both asynchronous and clock synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). The SCI3 can transmit and receive IrDA communication waveforms based on the Infrared Data Association (IrDA) standard version 1.0.
14.1
Features
* Choice of asynchronous or clock synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected * On-chip baud rate generator, internal clock, or external clock can be selected as a transfer clock source. * Six interrupt sources Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (The SCI3 is halted as the initial value. For details, refer to section 5.4, Module Standby Function.) Asynchronous mode * * * * * Data length: 7, 8, or 5 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RXD3 pin level directly in the case of a framing error
SCI0012A_000020020900
Rev. 3.00 May 15, 2007 Page 231 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Clock synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Note: When using serial communication interface 3, the system clock oscillator or subclock oscillator must be used. Figure 14.1 shows a block diagram of the SCI3.
SCK3
External clock Baud rate generator
Internal clock (/64, /16, w, )
BRC3 Clock
BRR3
SEMR Transmit/receive control circuit SMR3 SCR3 SSR3 TSR3 TDR3
Internal data bus
RSR3 SPCR TXD3 RXD3 IrCR
RDR3
Interrupt request (TEI3, TXI3, RXI3, ERI3)
[Legend] RSR3: Receive shift register 3 RDR3: Receive data register 3 TSR3: Transmit shift register 3 TDR3: Transmit data register 3 SMR3: Serial mode register 3 SCR3: Serial control register 3 SSR3: Serial status register 3 BRR3: Bit rate register 3 BRC3: Bit rate counter 3 SPCR: Serial port control register IrDA control register IrCR: SEMR: Serial extended mode register
Figure 14.1 Block Diagram of SCI3
Rev. 3.00 May 15, 2007 Page 232 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.2
Input/Output Pins
Table 14.1 shows the pin configuration of the SCI3. Table 14.1 Pin Configuration
Pin Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbreviation SCK3 RXD3 TXD3 I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output
14.3
Register Descriptions
The SCI3 has the following registers for each channel. * * * * * * * * * * * Receive shift register 3 (RSR3)* Receive data register 3 (RDR3)* Transmit shift register 3 (TSR3)* Transmit data register 3 (TDR3)* Serial mode register 3 (SMR3)* Serial control register 3 (SCR3)* Serial status register 3 (SSR3)* Bit rate register 3 (BRR3)* Serial port control register (SPCR) IrDA control register (IrCR) Serial extended mode register (SEMR)
Note: * These register names are abbreviated to RSR, RDR, TSR, TDR, SMR, SCR, SSR, and BRR in the text.
Rev. 3.00 May 15, 2007 Page 233 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.1
Receive Shift Register (RSR)
RSR is a shift register that receives serial data input from the RXD3 pin and converts it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 14.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI3 has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. RDR is initialized to H'00. RDR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode. 14.3.3 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD3 pin. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if the TDRE bit in SSR is set to 1). TSR cannot be directly accessed by the CPU. 14.3.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during transmission of one-frame data, the SCI3 transfers the written data to TSR to continue transmission. To achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is initialized to H'FF. TDR is initialized to H'FF by a reset or in standby mode, watch mode, or module standby mode.
Rev. 3.00 May 15, 2007 Page 234 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.5
Serial Mode Register (SMR)
SMR sets the SCI3's serial communication format and selects the clock source for the on-chip baud rate generator. SMR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Bit 7 Bit Name COM Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 or 5 bits as the data length. 1: Selects 7 or 5 bits as the data length. When 7-bit data is selected. the MSB (bit 7) in TDR is not transmitted. To select 5 bits as the data length, set 1 to both the PE and MP bits. The three most significant bits (bits 7, 6, and 5) in TDR are not transmitted. In clock synchronous mode, the data length is fixed to 8 bits regardless of the CHR bit setting. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. In clock synchronous mode, parity bit addition and checking is not performed regardless of the PE bit setting.
Rev. 3.00 May 15, 2007 Page 235 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit 4
Bit Name PM
Initial Value 0
R/W R/W
Description Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number, in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. When odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number, in reception, a check is carried out to confirm that the number of 1bits in the receive data plus the parity bit is an odd number. If parity bit addition and checking is disabled in clock synchronous mode and asynchronous mode, the PM bit setting is invalid.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
2
MP
0
R/W
5-Bit Communication When this bit is set to 1, the 5-bit communication format is enabled. Make sure to set bit 5 (PF) to 1 when setting this bit (MP) to 1.
Rev. 3.00 May 15, 2007 Page 236 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit 1 0
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W R/W
Description Clock Select 0 and 1 These bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: W clock (n = 0) 10: /16 clock (n = 2) 11: /64 clock (n = 3) When the setting value is 01 in subactive mode or subsleep mode, the SCI3 can be used only when W is selected for the CPU operating clock. For the relationship between the bit rate register setting and the baud rate, see section 14.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 14.3.8, Bit Rate Register (BRR)).
14.3.6
Serial Control Register (SCR)
SCR enables or disables SCI3 transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, refer to section 14.7, Interrupt Requests. SCR is initialized to H'00 by a reset or in standby mode, watch mode, or module standby mode.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI3 interrupt request is enabled. TXI3 can be released by clearing the TDRE it or TI bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, the RXI3 and ERI3 interrupt requests are enabled. RXI3 and ERI3 can be released by clearing the RDRF bit or the FER, PER, or OER error flag to 0, or by clearing the RIE bit to 0.
Rev. 3.00 May 15, 2007 Page 237 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit 5
Bit Name TE
Initial Value 0
R/W R/W
Description Transmit Enable When this bit is set to 1, transmission is enabled. When this bit is 0, the TDRE bit in SSR is fixed at 1. When transmit data is written to TDR while this bit is 1, Bit TDRE in SSR is cleared to 0 and serial data transmission is started. Be sure to carry out SMR settings, and setting of bit SPC3 in SPCR, to decide the transmission format before setting bit TE to 1.
4
RE
0
R/W
Receive Enable When this bit is set to 1, reception is enabled. In this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in clock synchronous mode. Be sure to carry out the SMR settings to decide the reception format before setting bit RE to 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state
3 2
MPIE TEIE
0 0
R/W R/W
Reserved Transmit End Interrupt Enable When this bit is set to 1, the TEI3 interrupt request is enabled. TEI3 can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by clearing bit TEIE to 0.
Rev. 3.00 May 15, 2007 Page 238 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 0 and 1 Select the clock source. Asynchronous mode: 00: Internal baud rate generator (SCK3 pin functions as an I/O port) 01: Internal baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK3 pin) 10: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK3 pin) 11: Reserved Clock synchronous mode: 00: Internal clock (SCK3 pin functions as clock output) 01: Reserved 10: External clock (SCK3 pin functions as clock input) 11: Reserved
Rev. 3.00 May 15, 2007 Page 239 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.7
Serial Status Register (SSR)
SSR consists of status flags of the SCI3. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. SSR is initialized to H'84 by a reset or in standby mode, watch mode, or module standby mode.
Bit 7 Bit Name TDRE Initial Value 1 R/W Description
R/(W)* Transmit Data Register Empty Indicates that transmit data is stored in TDR. [Setting conditions] * * * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR
[Clearing conditions]
6
RDRF
0
R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1
[Clearing conditions] * When data is read from RDR If an error is detected in reception, or if the RE bit in SCR has been cleared to 0, RDR and bit RDRF are not affected and retain their previous state. Note that if data reception is completed while bit RDRF is still set to 1, an overrun error (OER) will occur and the receive data will be lost.
Rev. 3.00 May 15, 2007 Page 240 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit 5
Bit Name OER
Initial Value 0
R/W
Description
R/(W)* Overrun Error [Setting condition] * * When an overrun error occurs in reception When 0 is written to OER after reading OER = 1 [Clearing condition] When bit RE in SCR is cleared to 0, bit OER is not affected and retains its previous state. When an overrun error occurs, RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with bit OER set to 1, and in clock synchronous mode, transmission cannot be continued either.
4
FER
0
R/(W)* Framing Error [Setting condition] * * When a framing error occurs in reception When 0 is written to FER after reading FER = 1 [Clearing condition] When bit RE in SCR is cleared to 0, bit FER is not affected and retains its previous state. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. When a framing error occurs, the receive data is transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER set to 1. In clock synchronous mode, neither transmission nor reception is possible when bit FER is set to 1.
Rev. 3.00 May 15, 2007 Page 241 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Bit 3
Bit Name PER
Initial Value 0
R/W
Description
R/(W)* Parity Error [Setting condition] * * When a parity error is generated during reception When 0 is written to PER after reading PER = 1 [Clearing condition] When bit RE in SCR is cleared to 0, bit PER is not affected and retains its previous state. * Receive data in which a parity error has occurred is still transferred to RDR, but bit RDRF is not set. Reception cannot be continued with bit PER set to 1. In clock synchronous mode, neither transmission nor reception is possible when bit PER is set to 1.
2
TEND
1
R
Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after reading TDRE = 1 When the transmit data is written to TDR
[Clearing conditions] * * 1 0 Note: * MPBR MPBT 0 0 R R/W
Reserved This bit is always read as 0 and cannot be modified. Reserved The write value should always be 0.
Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 242 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.8
Bit Rate Register (BRR)
BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF. Tables 14.2 and 14.3 show the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in asynchronous mode. Table 14.5 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in these tables are values in active (highspeed) mode. When the ABCS bit in SEMR is set to 1 in asynchronous mode, the maximum bit rate in table 14.5 is doubled. Table 14.6 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in clock synchronous mode. The values shown in table 14.6 are values in active (high-speed) mode. The N setting in BRR and error for other operating frequencies and bit rates can be obtained by the following formulas: [Asynchronous Mode and ABCS Bit is 0]
N= -1 32 x 22n x B
B (bit rate obtained from n, N, ) - R (bit rate in left-hand column in table 14.2) R (bit rate in left-hand column in table 14.2) x 100
Error (%) =
[Asynchronous Mode and ABCS Bit is 1]
N= -1 16 x 22n x B
B (bit rate obtained from n, N, ) - R (bit rate in left-hand column in table 14.3) R (bit rate in left-hand column in table 14.3) x 100
Error (%) =
[Legend] B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (Hz) n: Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 14.4)
Rev. 3.00 May 15, 2007 Page 243 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 0) (1)
32.8 kHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n 0 0 0 N 6 4 3 Error (%) -2.38 2.50 2.50 n 0 0 0 0 0 0 38.4 kHz N 10 7 5 3 1 0 Error (%) -0.83 0.00 0.00 0.00 0.00 0.00 n 2 2 2 0 0 0 0 0 0 0 2 MHz N 35 25 19 249 207 103 51 25 12 1 Error (%) -1.36 0.16 -2.34 0.00 0.16 0.16 0.16 0.16 0.16 0.00 n 2 2 2 2 0 0 0 0 0 0 -- -- -- 2.097152 MHz N 36 26 19 15 217 108 54 26 13 6 -- -- -- Error (%) 0.64 1.14 2.40 2.40 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- --
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 0) (2)
2.4576 MHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 2 0 0 0 0 0 0 0 -- 0 N 43 31 23 18 255 127 63 31 15 7 3 -- 1 Error (%) -0.83 0.00 0.00 1.05 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 2 2 2 0 0 0 0 0 0 0 -- 3 MHz N 52 38 28 22 19 155 77 38 19 9 4 2 -- Error (%) 0.50 0.16 1.02 1.90 -2.34 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- n 2 2 2 2 2 0 0 0 0 0 0 -- 0 3.6864 MHz N 64 47 35 28 23 191 95 47 23 11 5 -- 2 Error (%) 0.70 0.00 0.00 -0.69 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 n 2 2 2 2 2 0 0 0 0 0 -- 0 -- 4 MHz N 70 51 38 30 25 207 103 51 25 12 -- 3 -- Error (%) 0.03 0.16 0.16 0.81 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 --
Rev. 3.00 May 15, 2007 Page 244 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 0) (3)
4.194304 MHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 2 2 0 0 0 0 0 0 -- -- N 73 54 40 32 26 217 108 54 26 13 6 -- -- Error (%) 0.64 -0.70 -0.10 -0.70 1.14 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- -- n 2 2 2 2 2 0 0 0 0 0 0 0 0 4.9152 MHz N 86 63 47 37 31 255 127 63 31 15 7 4 3 Error (%) 0.31 0.00 0.00 1.05 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 2 2 2 0 0 0 0 0 0 0 5 MHz N 88 64 48 38 32 15 129 64 32 15 7 4 3 Error (%) -0.25 0.16 -0.35 0.16 -1.36 1.73 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 2 2 2 2 2 0 0 0 0 0 0 0 6 MHz N 106 77 58 46 38 19 155 77 38 19 9 5 4 Error (%) -0.44 0.16 -0.69 -0.27 0.16 -2.34 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 0) (4)
6.144 MHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 2 2 2 0 0 0 0 0 0 0 N Error (%) n 2 2 2 2 2 2 0 0 0 0 0 0 7.3728 MHz N Error (%) n 2 2 2 2 2 2 0 0 0 0 0 0 -- 8 MHz N Error (%) n 2 2 2 2 2 2 0 0 0 0 0 0 0 9.8304 MHz N Error (%) n 2 2 2 2 2 2 2 0 0 0 0 0 0 10 MHz N Error (%)
108 0.08 79 59 47 39 19 79 39 19 9 5 4 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
130 -0.07 95 71 57 47 23 95 47 23 11 5 0.00 0.00 -0.69 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00
141 0.03 103 0.16 77 62 51 25 0.16 -0.79 0.16 0.16
174 -0.26 127 0.00 95 76 63 31 0.00 -0.26 0.00 0.00
177 -0.25 129 0.16 97 77 64 32 15 64 32 15 9 7 -0.35 0.16 0.16 -1.36 1.73 0.16 -1.36 1.73 0.00 1.73
159 0.00
191 0.00
207 0.16 103 0.16 51 25 12 7 -- 0.16 0.16 0.16 0.00 --
255 0.00 127 0.00 63 31 15 9 7 0.00 0.00 0.00 -1.70 0.00
129 0.16
----
Rev. 3.00 May 15, 2007 Page 245 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 1) (1)
32.8 kHz Bit Rate (bit/s) 110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400 n N Error (%) n 38.4 kHz N Error (%) n 2 MHz N Error (%) n 2.097152 MHz N Error (%)
0 0 0 0 0 -- -- -- -- -- -- -- --
18 13 9 7 6 -- -- -- -- -- -- -- --
-1.91 -2.38 2.50 2.50 -2.38 -- -- -- -- -- -- -- --
0 0 0 -- 0 0 0 0 -- -- -- -- --
21 15 11 -- 7 3 1 0 -- -- -- -- --
-0.83 0.00 0.00 -- 0.00 0.00 0.00 0.00 -- -- -- -- --
2 2 2 2 2 0 0 0 0 0 -- 0 --
70 51 38 30 25 207 103 51 25 12 -- 3 --
0.03 0.16 0.16 0.81 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 --
2 2 2 2 2 0 0 0 0 0 0 -- --
73 54 40 32 26 217 108 54 26 13 6 -- --
0.64 -0.70 -0.10 -0.70 1.14 0.21 0.21 -0.70 1.14 -2.48 -2.48 -- --
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 1) (2)
2.4576 MHz Bit Rate (bit/s) n N Error (%) n 3 MHz N Error (%) n 3.6864 MHz N Error (%) n 4 MHz N Error (%)
110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400
2 2 2 2 2 0 0 0 0 0 0 0 0
86 63 47 37 31 255 127 63 31 15 7 4 3
0.31 0.00 0.00 1.05 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
2 2 2 2 2 2 0 0 0 0 0 0 0
106 77 58 46 38 19 155 77 38 19 9 5 4
-0.44 0.16 -0.69 -0.27 0.16 -2.34 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34
2 2 2 2 2 2 0 0 0 0 0 -- 0
130 95 71 57 47 23 191 95 47 23 11 -- 5
-0.07 0.00 0.00 -0.69 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00
2 2 2 2 2 2 0 0 0 0 0 0 --
141 103 77 62 51 25 207 103 51 25 12 7 --
0.03 0.16 0.16 -0.79 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 --
Rev. 3.00 May 15, 2007 Page 246 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 1) (3)
4.194304 MHz Bit Rate (bit/s) n N Error (%) n 4.9152 MHz N Error (%) n 5 MHz N Error (%) n 6 MHz N Error (%)
110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400
2 2 2 2 2 2 0 0 0 0 0 -- 0
148 108 81 65 54 26 217 108 54 26 13 -- 6
-0.04 0.21 -0.10 -0.70 -0.70 1.14 0.21 0.21 -0.70 1.14 -2.48 -- -2.48
2 2 2 2 2 2 0 0 0 0 0 0 0
174 127 95 76 63 31 255 127 63 31 15 9 7
-0.26 0.00 0.00 -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
2 2 2 2 2 2 2 0 0 0 0 0 0
177 129 97 77 64 32 15 129 64 32 15 9 7
-0.25 0.16 -0.35 0.16 0.16 -1.36 1.73 0.16 0.16 -1.36 1.73 0.00 1.73
2 2 2 2 2 2 2 0 0 0 0 0 0
212 155 116 93 77 38 19 155 77 38 19 11 9
0.03 0.16 0.16 -0.27 0.16 0.16 -2.34 0.16 0.16 0.16 -2.34 0.00 -2.34
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode and ABCS Bit is 1) (4)
6.144 MHz Bit Rate (bit/s) n N Error (%) n 7.3728 MHz N Error (%) n 8 MHz N Error (%) n 9.8304 MHz N Error (%) n 10 MHz N Error (%)
110 150 200 250 300 600 1200 2400 4800 9600 19200 31250 38400
2 2 2 2 2 2 2 0 0 0 0 0 0
217 159 119 95 79 39 19 159 79 39 19 11 9
0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00
3 2 2 2 2 2 2 0 0 0 0 0 0
64 191 143 114 95 47 23 191 95 47 23 14 11
0.70 0.00 0.00 0.17 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
3 2 2 2 2 2 2 0 0 0 0 0 0
70 207 155 124 103 51 25 207 103 51 25 15 12
0.03 0.16 0.16 0.00 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16
3 2 2 2 2 2 2 0 0 0 0 0 0
86 255 191 153 127 63 31 255 127 63 31 19 15
0.31 0.00 0.00 -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00
3 3 2 2 2 2 2 2 0 0 0 0 0
88 64 194 155 129 64 32 15 129 64 32 19 15
-0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.16 0.16 -1.36 0.00 1.73
Rev. 3.00 May 15, 2007 Page 247 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.4 Relation between n and Clock
SMR Setting n 0 0 2 3 Note: * Clock w* /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1
In subactive or subsleep mode, the SCI3 can be operated only when the CPU operating clock is W.
Table 14.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Maximum Bit Rate (bit/s) (MHz) 0.0328* 0.0384* 2 2.097152 2.4576 3 3.6864 4 4.194304 4.9152 5 6 6.144 7.3728 8 9.8304 10 Note: * ABCS = 0 1025 1200 62500 65536 76800 93750 115200 125000 131072 153600 156250 187500 192000 230400 250000 307200 312500 ABCS = 1 2050 2400 125000 131072 153600 187500 230400 250000 262144 307200 312500 375000 384000 460800 500000 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
When CKS1 = 0 and CKS0 = 1 in SMR
Rev. 3.00 May 15, 2007 Page 248 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (1)
Bit Rate (bit/s) 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M Note: * n 0 0 0 0 0 32.8 kHz N 40 32 26 15 7 Error (%) 0.00 -0.61 1.23 2.50 2.50 n 0 0 0 0 N 47 37 31 18 38.4 kHz Error (%) 0.00 1.05 0.00 1.05 n 2 2 2 2 2 0 0 0 0 0 0 0 0* N 155 124 103 62 30 199 99 49 19 9 4 1 0* 2 MHz Error (%) 0.16 0.00 0.16 -0.79 0.81 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00*
Continuous transmission/reception is not possible.
Rev. 3.00 May 15, 2007 Page 249 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) (2)
Bit Rate (bit/s) 200 250 300 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M Note: n 3 2 2 2 2 2 0 0 0 0 0 0 0 0* N 4 MHz Error (%) n 3 3 3 2 2 2 2 0 0 0 0 0 0 0 N 77 0.16 249 0.00 207 0.16 124 0.00 62 -0.79 24 0.00 199 0.00 99 0.00 39 0.00 19 0.00 9 0.00 3 0.00 1 0.00 0* 0.00* 8 MHz Error (%) n 3 3 3 3 2 2 2 0 0 0 0 0 0 N 194 155 129 77 155 62 30 249 99 49 24 9 4 155 0.16 124 0.00 103 0.16 249 0.00 124 0.00 49 0.00 24 0.00 199 0.00 79 0.00 39 0.00 19 0.00 7 0.00 3 0.00 1 0.00 10 MHz Error (%) 0.16 0.16 0.16 0.16 0.16 -0.79 0.81 0.00 0.00 0.00 0.00 0.00 0.00
* Continuous transmission/reception is not possible. The value set in BRR is given by the following formula:
N= -1 4 x 22n x B
B: N: : n:
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (Hz) Baud rate generator input clock number (n = 0, 2, or 3) (The relation between n and the clock is shown in table 14.7.)
Table 14.7 Relation between n and Clock
SMR Setting n 0 0 2 3 Note: * Clock W* /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1
In subactive or subsleep mode, the SCI3 can be operated only when the CPU operating clock is W.
Rev. 3.00 May 15, 2007 Page 250 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.9
Serial Port Control Register (SPCR)
SPCR selects the function of the TXD3 (IrTXD) pin and whether to invert the input/output data of the RXD3 (IrRXD) and TXD3 (IrTXD) pins.
Bit 7, 6 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 5 4 SPC3 0 0 R/W Reserved This bit is always read as 0 and cannot be modified. P32/TXD3/IrTXD Pin Function Switch Selects whether pin P32/TXD3/IrTXD is used as P32 or as TXD3/IrTXD. 0: P32 I/O pin 1: TXD3/IrTXD output pin Set the TE bit in SCR after setting this bit to 1. 3, 2 All 0 Reserved These bits are always read as 0 and cannot be modified. 1 SCINV1 0 R/W TXD3/IrTXD Pin Output Data Inversion Switch Selects whether output data of the TXD3/IrTXD pin is inverted or not. 0: Output data of TXD3/IrTXD pin is not inverted. 1: Output data of TXD3/IrTXD pin is inverted. 0 SCINV0 0 R/W RXD3/IrRXD Pin Input Data Inversion Switch Selects whether input data of the RXD3/IrRXD pin is inverted or not. 0: Input data of RXD3/IrRXD pin is not inverted. 1: Input data of RXD3/IrRXD pin is inverted. Note: When the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. When modifying the serial port control register, modification must be made in a state in which data changes are invalidated.
Rev. 3.00 May 15, 2007 Page 251 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.10
IrDA Control Register (IrCR)
IrCR controls the IrDA operation of the SCI3.
Bit 7 Bit Name IrE Initial Value 0 R/W R/W Description IrDA Enable Selects whether the SCI3 I/O pins function as the SCI3 or IrDA. 0: TXD3/IrTXD and RXD3/IrRXD pins function as TXD3 and RXD3 1: TXD3/IrTXD and RXD3/IrRXD pins function as IrTXD and IrRXD 6 5 4 IrCKS2 IrCKS1 IrCKS0 0 0 0 R/W R/W R/W IrDA Clock Select If the IrDA function is enabled, these bits set the highpulse width when encoding the IrTXD output pulse. 000: Bit rate x 3/16 001: /2 010: /4 011: /8 100: /16 101: Setting prohibited 11x: Setting prohibited 3 to 0 All 0 Reserved These bits are always read as 0 and cannot be modified. [Legend] x: Don't care.
Rev. 3.00 May 15, 2007 Page 252 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.11
Serial Extended Mode Register (SEMR)
SEMR sets the basic clock used in asynchronous mode.
Bit 7 to 4 Bit Name Initial Value All 0 R/W Description Reserved These bits are always read as 0 and cannot be modified. 3 ABCS 0 R/W Asynchronous Mode Basic Clock Select Selects the basic clock for the bit period in asynchronous mode. This setting is enabled only in asynchronous mode (COM bit in SMR3 is 0). 0: Operates on a basic clock with a frequency of 16 times the transfer rate 1: Operates on a basic clock with a frequency of eight times the transfer rate Clear the ABCS bit to 0, when the IrDA function is enabled. 2 to 0 All 0 Reserved These bits are always read as 0 and cannot be modified.
14.4
Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous mode, synchronization is performed at the falling edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. When the ABCS bit in SEMR is 1, the data is sampled on the 4th pulse of a clock with a frequency eight times the bit period. Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. Table 14.8 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in SMR as shown in table 14.9.
Rev. 3.00 May 15, 2007 Page 253 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
LSB Serial Start data bit 1 bit Transmit/receive data 5, 7, or 8 bits
MSB Parity bit 1 bit, or none Stop bit 1 or 2 bits
1 Mark state
One unit of transfer data (character or frame)
Figure 14.2 Data Format in Asynchronous Communication 14.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3's serial clock source, according to the setting of the COM bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK3 pin, the clock frequency should be 16 times the bit rate used (when the ABCS bit in SEMR is 1, the clock frequency should be eight times the bit rate used). For details on selection of the clock source, see table 14.10. When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transfer data, as shown in figure 14.3.
Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 character (frame)
Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 3.00 May 15, 2007 Page 254 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.8 Data Transfer Formats (Asynchronous Mode)
SMR CHR 0 PE 0 MP 0 STOP 0 1
START
Serial Data Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10
STOP
11
12
8-bit data
0
0
0
1
START
8-bit data
STOP
STOP
0
0
1
0
Setting prohibited
0
0
1
1
Setting prohibited
0
1
0
0
START
8-bit data
P
STOP
0
1
0
1
START
8-bit data
P
STOP
STOP
0
1
1
0
START
5-bit data
STOP
0
1
1
1
START
5-bit data
STOP
STOP
1
0
0
0
START
7-bit data
STOP
1
0
0
1
START
7-bit data
STOP
STOP
1
0
1
0
Setting prohibited
1
0
1
1
Setting prohibited
1
1
0
0
START
7-bit data
P
STOP
1
1
0
1
START
7-bit data
P
STOP
STOP
1
1
1
0
START
5-bit data
P
STOP
1 [Legend]
1
1
1
START
5-bit data
P
STOP
STOP
START: Start bit STOP: P: Stop bit Parity bit
Rev. 3.00 May 15, 2007 Page 255 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.9 SMR Settings and Corresponding Data Transfer Formats
SMR Bit 7 COM 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 0 1 1 x 0 x x Clock synchronous mode 8-bit data No 5-bit data Yes 1 bit 2 bits No Setting prohibited 5-bit data No 1 bit 2 bits Setting prohibited Yes 7-bit data No Mode Asynchronous mode Data Length 8-bit data Data Transfer Format Parity Bit No Stop Bit Length 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits
[Legend]
x: Don't care.
Rev. 3.00 May 15, 2007 Page 256 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Table 14.10 SMR and SCR Settings and Clock Source Selection
SMR Bit 7 COM 0 Bit 1 CKE1 0 SCR Bit 0 CKE0 0 1 1 1 0 1 0 1 1 Note: * 1 0 1 0 0 0 1 1 1 When the ABCS bit in SEMR is 1, inputs a clock with a frequency eight times the bit rate. Mode Asynchronous mode Transmit/Receive Clock Clock Source Internal SCK Pin Function I/O port (SCK3 pin not used) Outputs a clock with the same frequency as the bit rate External Clock synchronous Internal mode External Inputs a clock with a frequency 16 times the bit rate* Outputs the serial clock Inputs the serial clock
Reserved (Do not specify these combinations)
Rev. 3.00 May 15, 2007 Page 257 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.4.2
SCI3 Initialization
Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. When the external clock is used in clock synchronous mode, the clock must not be supplied during initialization.
Start initialization
[1]
Clear TE and RE bits in SCR to 0
Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, clock is output immediately after CKE1 and CKE0 settings are made. When the clock output is selected at reception in clock synchronous mode, clock is output immediately after CKE1, CKE0, and RE are set to 1.
Set CKE1 and CKE0 bits in SCR3
[1]
Set data transfer format in SMR
[2]
Set value in BRR Wait
[3] [2] No [3]
Set the data transfer format in SMR. Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Setting bits TE and RE enables the TXD3 and RXD3 pins to be used. Also set the RIE, TIE, and TEIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit.
1-bit interval elapsed? Yes Set SPC3 bit in SPCR to 1 Set TE and RE bits in SCR to 1, and set RIE, TIE and TEIE bits.
[4]
[4]

Figure 14.4 Sample SCI3 Initialization Flowchart
Rev. 3.00 May 15, 2007 Page 258 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.4.3
Data Transmission
Figure 14.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI3 interrupt request is generated. Continuous transmission is possible because the TXI3 interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. The SCI3 checks the TDRE flag at the timing for sending the stop bit. 4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. 6. Figure 14.6 shows a sample flowchart for transmission in asynchronous mode.
Start bit Serial data 1 0 D0 D1 1 frame Transmit data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1
TDRE TEND LSI TXI3 interrupt operation request generated User processing TDRE flag cleared to 0 Data written to TDR TXI3 interrupt request generated TEI3 interrupt request generated
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
Rev. 3.00 May 15, 2007 Page 259 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start transmission Set SPC3 bit in SPCR to 1
[1]
[1]
Read TDRE flag in SSR
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. (After the TE bit is set to 1, one frame of 1 is output, then transmission is possible.) To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear the SPC3 bit in SPCR and the TE bit in SCR to 0.
No TDRE = 1 Yes Write transmit data to TDR [3] [2]
[2]
Yes All data transmitted? No Read TEND flag in SSR
Note: * When the SPC3 bit in SPCR is cleared to 0, the pin functions as an I/O port. No
TEND = 1 Yes No Break output? Yes Clear PDR to 0 and set PCR to 1
[3]
Clear SPC3 bit in SPCR and TE bit in SCR to 0*
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
Rev. 3.00 May 15, 2007 Page 260 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.4.4
Serial Data Reception
Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit. * Parity check The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit PM in the serial mode register (SMR). * Stop bit check The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked. * Status check The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated. Receive data is not transferred to RDR. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is generated. Continuous reception is possible because the RXI3 interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed.
Rev. 3.00 May 15, 2007 Page 261 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start bit Serial data 1 0 D0 D1
Receive data D7 1 frame
Parity Stop Start bit bit bit 0/1 1 0 D0
Receive data D1 1 frame D7
Parity Stop bit bit 0/1 0
Mark state (idle state) 1
RDRF FER LSI operation User processing
RXI3 interrupt request generated
RDRF flag cleared to 0 RDR data read
0 stop bit detected
ERI request in response to framing error Framing error processing
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) Table 14.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.8 shows a sample flowchart for serial data reception. Table 14.11 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception. However, note that if RDR is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, the RDRF flag will be cleared to 0.
Rev. 3.00 May 15, 2007 Page 262 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start reception
Read OER, PER, and FER flags in SSR
[1]
Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR No RDRF = 1 Yes [2]
Read receive data in RDR
[1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically. [3] To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and read RDR. The RDRF flag is cleared automatically. [4] If a receive error occurs, read the OER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the OER, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the RXD3 pin.
Yes All data received? (A) No Clear RE bit in SCR to 0 [3]
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)
Rev. 3.00 May 15, 2007 Page 263 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
[4] Error processing
No OER = 1 Yes Overrun error processing
No FER = 1 Yes Yes Break? No Framing error processing
No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0

Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2)
Rev. 3.00 May 15, 2007 Page 264 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5
Operation in Clock Synchronous Mode
Figure 14.9 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clock synchronous mode, the SCI3 receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clock synchronous mode, no parity bit is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer.
8-bit One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 14.9 Data Format in Clock Synchronous Communication 14.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM bit in SMR and CKE0 and CKE1 bits in SCR. When the SCI3 is operated on an internal clock, the serial clock is output from the SCK3 pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 14.5.2 SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample flowchart in figure 14.4.
Rev. 3.00 May 15, 2007 Page 265 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.3
Serial Data Transmission
Figure 14.10 shows an example of SCI3 operation for transmission in clock synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI3 interrupt request is generated. 3. 8-bit data is sent from the TXD3 pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD3 pin. 4. The SCI3 checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI3 interrupt request is generated. 7. The SCK3 pin is fixed high. Figure 14.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission.
Serial clock Serial data Bit 0 Bit 1 1 frame TDRE TEND LSI TXI3 operation interrupt request generated User processing TDRE flag cleared to 0 Data written to TDR TXI3 interrupt request generated TEI3 interrupt request generated Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7
Figure 14.10 Example of SCI3 Operation in Transmission in Clock Synchronous Mode
Rev. 3.00 May 15, 2007 Page 266 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start transmission
Set SPC3 bit in SPCR to 1
[1]
[1]
Read TDRE flag in SSR
No TDRE = 1 [2] Yes
Write transmit data to TDR
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When clock output is selected and data is written to TDR, clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
[2]
All data transmitted? No
Yes
Read TEND flag in SSR
No TEND = 1 Yes Clear TE bit in SCR to 0
Figure 14.11 Sample Serial Transmission Flowchart (Clock Synchronous Mode)
Rev. 3.00 May 15, 2007 Page 267 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.4
Serial Data Reception (Clock Synchronous Mode)
Figure 14.12 shows an example of SCI3 operation for reception in clock synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. The SCI3 stores the received data in RSR. 3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is generated.
Serial clock
Serial data
Bit 7
Bit 0 1 frame
Bit 7
Bit 0
Bit 1 1 frame
Bit 6
Bit 7
RDRF
OER LSI operation User processing RXI3 interrupt request generated RDRF flag cleared to 0 RDR data read RXI3 interrupt request generated RDR data has not been read (RDRF = 1) ERI3 interrupt request generated by overrun error Overrun error processing
Figure 14.12 Example of SCI3 Reception Operation in Clock Synchronous Mode Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flowchart for serial data reception.
Rev. 3.00 May 15, 2007 Page 268 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Start reception [1] Read OER flag in SSR [1] [2] Yes OER = 1? [4] No Overrun error processing (Continued below) Read RDRF flag in SSR [2] [4] RDRF = 1? Yes [3] Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag and reading RDR should be finished. When data is read from RDR, the RDRF flag is automatically cleared to 0. If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Reception cannot be resumed if the OER flag is set to 1.
No
Read receive data in RDR
Yes Data reception continued? No Clear RE bit in SCR to 0 [3]
[4]
Start overrun error processing
Overrun error processing
Clear OER flag in SSR to 0
Figure 14.13 Sample Serial Reception Flowchart (Clock Synchronous Mode)
Rev. 3.00 May 15, 2007 Page 269 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.5
Simultaneous Serial Data Transmission and Reception
Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Start transmission/reception Set SPC3 bit in SPCR to 1
[1] [1]
Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR
Read OER flag in SSR Yes [4] Overrun error processing
OER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR
[2]
Yes
Data transmission/reception continued? No Clear TE and RE bits in SCR to 0
[3]
Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. [2] Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0. [3] To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. When data is read from RDR, the RDRF flag is automatically cleared to 0. [4] If an overrun error occurs, read the OER flag in SSR, and after performing the appropriate error processing, clear the OER flag to 0. Transmission/reception cannot be resumed if the OER flag is set to 1. For overrun error processing, see figure 14.13.
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clock Synchronous Mode)
Rev. 3.00 May 15, 2007 Page 270 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.6
IrDA Operation
IrDA operation can be used with the SCI3. Figure 14.15 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in IrCR, the TXD3 and RXD3 pins in the SCI3 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTXD and IrRXD pins). Connecting these pins to the infrared data transceiver/receiver achieves infrared data communication based on the system defined by the IrDA standard version 1.0. In the system defined by the IrDA standard version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified as required. The IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate; the transfer rate must be modified through programming.
IrDA TXD3/IrTXD RXD3/IrRXD Phase inversion Phase inversion Pulse encoder Pulse decoder TXD RXD SCI3
IrCR
Figure 14.15 IrDA Block Diagram
Rev. 3.00 May 15, 2007 Page 271 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.6.1
Transmission
During transmission, the output signals from the SCI3 (UART frames) are converted to IR frames using the IrDA interface (see figure 14.16). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in IrCR. According to the standard, the high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) +1.08 s at maximum. For example, when the frequency of system clock is 10 MHz, being equal to or greater than 1.41 s, the high-level pulse width at minimum can be specified as 1.6 s. For serial data of level 1, no pulses are output.
UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1
0
Transmission IR frame Start bit 0 1 0 1 0 Data
Reception
Stop bit 1 1 0 1
0
Bit cycle
Pulse width is 1.6 s to 3/16 bit cycle
Figure 14.16 IrDA Transmission and Reception
Rev. 3.00 May 15, 2007 Page 272 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.6.2
Reception
During reception, IR frames are converted to UART frames using the IrDA interface before inputting to the SCI3. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 s, the minimum width allowed, the pulse is recognized as level 0. 14.6.3 High-Level Pulse Width Selection
Table 14.12 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 14.12 IrCKS2 to IrCKS0 Bit Settings
Operating Frequency (MHz) 2 2.097152 2.4576 3 3.6864 4.9152 5 6 6.144 7.3728 8 9.8304 10 2400 78.13 010 010 010 011 011 011 011 100 100 100 100 100 100 Bit Rate (bps) (Upper Row) / Bit Interval x 3/16 (s) (Lower Row) 9600 19.53 010 010 010 011 011 011 011 100 100 100 100 100 100 19200 9.77 010 010 010 011 011 011 011 100 100 100 100 100 100 38400 4.88 010 010 010 011 011 011 011 100 100 100 100 100 100
Rev. 3.00 May 15, 2007 Page 273 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.7
Interrupt Requests
The SCI3 creates the following six interrupt requests: transmit end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.13 shows the interrupt sources. Table 14.13 SCI3 Interrupt Requests
Interrupt Requests Receive Data Full Transmit Data Empty Transmission End Receive Error Abbreviation RXI TXI TEI ERI Interrupt Sources Setting RDRF in SSR Setting TDRE in SSR Setting TEND in SSR Setting OER, FER, and PER in SSR
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR. When the TDRE bit in SSR is set to 1, a TXI3 interrupt is requested. When the TEND bit in SSR is set to 1, a TEI3 interrupt is requested. These two interrupts are generated during transmission. The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR is set to 1 before transferring the transmit data to TDR, a TXI3 interrupt request is generated even if the transmit data is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR is set to 1 before transferring the transmit data to TDR, a TEI3 interrupt request is generated even if the transmit data has not been sent. It is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the generation of these interrupt requests (TXI3 and TEI3), clear the enable bits (TIE and TEIE) that correspond to these interrupt requests to 0, after transferring the transmit data to TDR. When the RDRF bit in SSR is set to 1, an RXI3 interrupt is requested, and if any of bits OER, PER, and FER is set to 1, an ERI3 interrupt is requested. These two interrupt requests are generated during reception. The SCI3 can carry out continuous reception using an RXI3 and continuous transmission using a TXI3.
Rev. 3.00 May 15, 2007 Page 274 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
These interrupts are shown in table 14.14. Table 14.14 Transmit/Receive Interrupts
Interrupt RXI3 Flags RDRF RIE Interrupt Request Conditions
When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, an RXI3 is enabled and an interrupt is requested. (See figure 14.17 (a).) When TSR is found to be empty (on completion of the previous transmission) and the transmit data placed in TDR is transferred to TSR, bit TDRE is set to 1. If bit TIE is set to 1 at this time, a TXI3 is enabled and an interrupt is requested. (See figure 14.17 (b).) When the last bit of the character in TSR is transmitted, if bit TDRE is set to 1, bit TEND is set to 1. If bit TEIE is set to 1 at this time, a TEI3 is enabled and an interrupt is requested. (See figure 14.17 (c).)
Notes
The RXI3 interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0. Continuous reception can be performed by repeating the above operations until reception of the next RSR data is completed. The TXI3 interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0. Continuous transmission can be performed by repeating the above operations until the data transferred to TSR has been transmitted. A TEI3 indicates that the next transmit data has not been written to TDR when the last bit of the transmit character in TSR is transmitted.
TXI3
TDRE TIE
TEI31
TEND TEIE
Rev. 3.00 May 15, 2007 Page 275 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
RDR
RDR
RSR (reception in progress) RXD3 pin RXD3 pin
RSR (reception completed, transfer)
RDRF = 0
RDRF
(RXI3 request when RIE = 1)
Figure 14.17 (a) RDRF Setting and RXI Interrupt
TDR (next transmit data) TDR
TSR (transmission in progress) TXD3 pin TXD3 pin
TSR (transmission completed, transfer)
TDRE = 0
TDRE
1
(TXI3 request when TIE = 1)
Figure 14.17 (b) TDRE Setting and TXI Interrupt
TDR TDR
TSR (transmission in progress) TXD3 pin TXD3 pin
TSR (transmission completed)
TEND = 0
TEND
(TEI3 request when TEIE = 1)
Figure 14.17 (c) TEND Setting and TEI Interrupt
Rev. 3.00 May 15, 2007 Page 276 of 516 REJ09B0152-0300
1
1
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8
14.8.1
Usage Notes
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD3 pin value directly. In a break, the input from the RXD3 pin becomes all 0, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 14.8.2 Mark State and Break Sending
When the SPC3 bit in SPCR is 0, the TXD3 pin functions as an I/O port whose direction (input or output) and level are determined by PCR and PDR, regardless of the TE setting. This can be used to set the TXD3 pin to the mark state (high level) or send a break during data transmission. To maintain the communication line at the mark state until the SPC3 bit in SPCR is set to 1, set both PCR and PDR to 1. As the SPC3 bit in SPCR is cleared to 0 at this point, the TXD3 pin functions as an I/O port, and 1 is output from the TXD3 pin. To send a break during data transmission, first set PCR to 1 and PDR to 0, and then clear the SPC3 and TE bits to 0. When the TE bit is cleared to 0 directly after the SPC3 bit is cleared to 0, the transmitter is initialized regardless of the current transmission state after the TE bit is cleared, the TXD3 pin functions as an I/O port after the SPC3 bit is cleared, and 0 is output from the TXD3 pin. 14.8.3 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
Rev. 3.00 May 15, 2007 Page 277 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.18. Thus, the reception margin in asynchronous mode is given by formula (1) below.
1 D - 0.5 M = (0.5 - )- - (L - 0.5) F x 100(%) 2N N
... Formula (1)
Where N: D: L: F:
Ratio of bit rate to clock (N = 16) Clock duty (D = 0.5 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula.
M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
16 clocks 8 clocks 0 Internal basic clock Receive data (RXD3) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0
Start bit
D0
D1
Figure 14.18 Receive Data Sampling Timing in Asynchronous Mode
Rev. 3.00 May 15, 2007 Page 278 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.5
Note on Switching SCK3 Pin Function
If the SCK3 pin is used as a clock output pin by the SCI3 in clock synchronous mode and is then switched to a general input/output pin (a pin with a different function), the SCK3 pin outputs a low level signal for half a system clock () cycle immediately after it is switched. This can be prevented by either of the following methods according to the situation. (1) When SCK3 Pin Function is Switched from Clock Output to Non Clock-Output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR to 1 and 0, respectively. In this case, bit COM in SMR should be left 1. The above prevents the SCK3 pin from being used as a general input/output pin. To avoid an intermediate level of voltage from being applied to the SCK3 pin, the line connected to the SCK3 pin should be pulled up to the VCC level via a resistor, or supplied with output from an external device. (2) When SCK3 Pin Function is Switched from Clock Output to General Input/Output
When stopping data transfer, 1. Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR to 1 and 0, respectively. 2. Clear bit COM in SMR to 0 3. Clear bits CKE1 and CKE0 in SCR to 0. Note that special care is also needed here to avoid an intermediate level of voltage from being applied to the SCK3 pin. 14.8.6 Relation between Writing to TDR and Bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When the SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost if it has not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR only once (not two or more times).
Rev. 3.00 May 15, 2007 Page 279 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.7
Relation between RDR Reading and bit RDRF
In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if RDR is read more than once, the second and subsequent read operations will be performed while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. This is shown in figure 14.19.
Frame 1 Frame 2 Frame 3
Communication line
Data 1
Data 2
Data 3
RDRF
RDR
Data 1 (A)
RDR read
Data 2 (B)
RDR read
Data 1 is read at point (A) Data 2 is read at point (B)
Figure 14.19 Relation between RDR Read Timing and Data In this case, only a single RDR read operation (not two or more) should be performed after first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clock synchronous mode, or before the STOP bit is transferred in asynchronous mode.
Rev. 3.00 May 15, 2007 Page 280 of 516 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.8
Transmit and Receive Operations when Making State Transition
Make sure that transmit and receive operations have completely finished before carrying out state transition processing. 14.8.9 Setting in Subactive or Subsleep Mode
In subactive or subsleep mode, the SCI3 can operate only when the CPU clock is W. The SA1 and SA0 bits in SYSCR2 should be set to 1. 14.8.10 Oscillator when Serial Communication Interface 3 is Used
When serial communication interface 3 is used, the system clock oscillator or subclock oscillator must be used. Do not use the on-chip oscillator. For details on selecting the system clock oscillator or on-chip oscillator, see section 4.2.4, On-Chip Oscillator Selection Method. For details on selecting the subclock oscillator or on-chip oscillator, see section 4.1.1, Oscillator Control Register (OSCCR).
Rev. 3.00 May 15, 2007 Page 281 of 518 REJ09B0152-0300
Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Rev. 3.00 May 15, 2007 Page 282 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Section 15 Synchronous Serial Communication Unit (SSU)
The synchronous serial communication unit (SSU) can handle clocked synchronous serial data communication. Figure 15.1 shows a block diagram of the SSU.
15.1
Features
* Can be operated in clocked synchronous communication mode or four-line bus communication mode (including bidirectional communication mode) * Can be operated as a master or a slave device * Choice of eight internal clocks (/256, /128, /64, /32, /16, /8, /4, and SUB/2) and an external clock as a clock source * Clock polarity and phase of SSCK can be selected * Choice of data transfer direction (MSB-first or LSB-first) * Receive error detection: overrun error * Multimaster error detection: conflict error * Five interrupt sources: transmit-end, transmit-data-empty, receive-data-full, overrun error, and conflict error * Continuous transmission and reception of serial data are enabled since both transmitter and receiver have buffer structure * Use of module standby mode enables this module to be placed in standby mode independently when not used. (The SSU is halted as the initial value. For details, refer to section 5.4, Module Standby Function.)
SCIAAU1A_000120030300
Rev. 3.00 May 15, 2007 Page 283 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Internal clock SSCK
Multiplexer
SSMR SSCRL
SCS
Transmission/ reception control circuit
SSCRH SSER SSSR
SSTDR SSO SSI Selector
SSTRSR
SSRDR
[Legend] SSMR: SSCRL: SSCRH: SSER: SSSR: SSTDR: SSTRSR: SSRDR: SS mode register SS control register L SS control register H SS enable register SS status register SS transmit data register SS shift register SS receive data register
Interrupt request (TXI, TEI, RXI, OEI, CEI)
Figure 15.1 Block Diagram of SSU
15.2
Input/Output Pins
Table 15.1 shows the pin configuration of the SSU. Table 15.1 Pin Configuration
Pin Name SSU clock SSU data input/output SSU data input/output SSU chip select input/output Abbreviation SSCK SSI SSO SCS I/O I/O I/O I/O I/O Function SSU clock input/output SSU data input/output SSU data input/output SSU chip select input/output
Rev. 3.00 May 15, 2007 Page 284 of 516 REJ09B0152-0300
Internal data bus
Section 15 Synchronous Serial Communication Unit (SSU)
15.3
Register Descriptions
The SSU has the following registers. * * * * * * * * SS control register H (SSCRH) SS control register L (SSCRL) SS mode register (SSMR) SS enable register (SSER) SS status register (SSSR) SS receive data register (SSRDR) SS transmit data register (SSTDR) SS shift register (SSTRSR) SS Control Register H (SSCRH)
15.3.1
SSCRH is a register that selects a master or a slave device, enables bidirectional mode, selects open-drain output of the serial data output pin, selects an output value of the serial data output pin, selects the SSCK pin, and selects the SCS pin.
Bit 7 Bit Name MSS Initial Value 0 R/W R/W Description Master/Slave Device Select Selects whether this module is used as a master device or a slave device. When this module is used as a master device, transfer clock is output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. 0: Operates as a slave device 1: Operates as a master device 6 BIDE 0 R/W Bidirectional Mode Enable Selects whether the serial data input pin and the output pin are both used or only one pin is used. For details, refer to section 15.4.3, Relationship between Data Input/Output and Shift Register. When the SSUMS bit in SSCRL is 0, this setting is invalid. 0: Normal mode. Communication is performed by using two pins. 1: Bidirectional mode. Communication is performed by using only one pin.
Rev. 3.00 May 15, 2007 Page 285 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Bit 5
Bit Name SOOS
Initial Value 0
R/W R/W
Description Serial Data Open-Drain Output Select Selects whether the serial data output pin is CMOS output or NMOS open-drain output. The serial data output pin is changed according to the register setting value. For details, refer to section 15.4.3, Relationship between Data Input/Output and Shift Register. 0: CMOS output 1: NMOS open-drain output
4
SOL
0
R/W
Serial Data Output Level Setting Although the value in the last bit of transmit data is retained in the serial data output after the end of transmission, the output level of serial data can be changed by manipulating this bit before or after transmission. When the output level is changed, the SOLP bit should be cleared to 0 and the MOV instruction should be used. If this bit is written during data transfer, erroneous operation may occur. Therefore this bit must not be manipulated during transmission. 0: Shows serial data output level to low in reading. Changes serial data output level to low in writing 1: Shows serial data output level to high in reading. Changes serial data output level to high in writing
3
SOLP
1
R/W
SOL Write Protect When output level of serial data is changed, the MOV instruction is used to set the SOL bit to 1 and clear this bit to 0 or to clear the SOL bit and this bit to 0. 0: In writing, output level can be changed according to the value of the SOL bit. 1: In reading, this bit is always read as 1. In writing, output level cannot be changed. (See section 15.5, Usage Note.)
Rev. 3.00 May 15, 2007 Page 286 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Bit 2
Bit Name SCKS
Initial Value 0
R/W R/W
Description SSCK Pin Select Selects whether the SSCK pin functions as a port or a serial clock pin. 0: Functions as a port 1: Functions as a serial clock pin
1 0
CSS1 CSS0
0 0
R/W R/W
SCS Pin Select Selects whether the SCS pin functions as a port, an SCS input, or SCS output. When the SSUMS bit in SSCRL is 0, the SCS pin functions as a port regardless of the setting of this bit. 00: Functions as a port 01: Functions as an SCS input 1x: Functions as an SCS output (however, functions as an SCS input before starting transfer)
[Legend] x: Don't care.
15.3.2
SS Control Register L (SSCRL)
SSCRL is a register that controls mode, software reset, and open-drain output of the SSCK and SCS pins.
Bit 7 Bit Name -- Initial Value 0 R/W -- Description Reserved This bit is always read as 0.
Rev. 3.00 May 15, 2007 Page 287 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Bit 6
Bit Name SSUMS
Initial Value 0
R/W R/W
Description SSU Mode Select Selects which combination of the serial data input pin and serial data output pin is used. For details, refer to section 15.4.3, Relationship between Data Input/Output and Shift Register. 0: Clocked synchronous communication mode Data input: SSI pin, Data output: SSO pin 1: Four-line bus communication mode When MSS = 1 and BIDE = 0 in SSCRH: Data input: SSI pin, Data output: SSO pin When MSS = 0 and BIDE = 0 in SSCRH: Data input: SSO pin, Data output: SSI pin When BIDE = 1 in SSCRH: Data input and output: SSO pin
5
SRES
0
R/W
Software Reset When this bit is set to 1, the SSU internal sequencer is forcibly reset. Then this bit is automatically cleared. The register value in the SSU is retained.
4
SCKOS
0
R/W
SSCK Pin Open-Drain Output Select Selects whether the SSCK pin functions as CMOS output or NMOS open-drain output. 0: CMOS output 1: NMOS open-drain output
3
CSOS
0
R/W
SCS Pin Open-Drain Output Select Selects whether the SCS pin functions as CMOS output or NMOS open-drain output. 0: CMOS output 1: NMOS open-drain output
2 to 0
All 0
Reserved These bits are always read as 0.
Rev. 3.00 May 15, 2007 Page 288 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.3.3
SS Mode Register (SSMR)
SSMR is a register that selects MSB-first or LSB-first, clock polarity, clock phase, and transfer clock rate.
Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select Selects whether data transfer is performed in MSB-first or LSB-first. 0: LSB-first 1: MSB-first 6 CPOS 0 R/W Clock Polarity Select Selects the clock polarity of SSCK. 0: Idle state = high 1: Idle state = low 5 CPHS 0 R/W Clock Phase Select Selects the clock phase of SSCK. 0: Data change at first edge 1: Data latch at first edge 4, 3 2 1 0 CKS2 CKS1 CKS0 All 0 0 0 0 R/W R/W R/W Reserved These bits are always read as 0. Transfer clock rate select Sets transfer clock rate (prescaler division ratio) when the internal clock is selected. The system clock () is halted in subactive mode or subsleep mode. Select SUB/2 in these modes. 000: /256 001: /128 010: /64 011: /32 100: /16 101: /8 110: /4 111: SUB/2
Rev. 3.00 May 15, 2007 Page 289 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.3.4
SS Enable Register (SSER)
SSER is a register that sets transmit enable, receive enable, and interrupt enable.
Bit 7 6 5 Bit Name TE RE RSSTP Initial Value 0 0 0 R/W R/W R/W R/W Description Transmit enable When this bit is 1, transmit operation is enabled. Receive enable When this bit is 1, receive operation is enabled. Receive single stop When this bit is 1, receive operation is completed after receiving one byte. 4 3 -- TEIE 0 0 -- R/W Reserved This bit is always read as 0. Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. 2 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. 1 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, an RXI and an OEI interrupt requests are enabled. 0 CEIE 0 R/W Conflict Error Interrupt Enable When this bit is set to 1, a CEI interrupt request is enabled.
Rev. 3.00 May 15, 2007 Page 290 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.3.5
SS Status Register (SSSR)
SSSR is a register that sets interrupt flags.
Bit 7 6 Bit Name -- ORER Initial Value 0 0 R/W -- R/(W)* Description Reserved This bit is always read as 0. Overrun Error Flag Indicates that the RDRF bit is abnormally terminated in reception because an overrun error has occurred. SSRDR retains received data before the overrun error occurs and the received data after the overrun error occurs is lost. When this bit is set to 1, subsequent serial reception cannot be continued. When the MSS bit in SSCRH is 1, this is also applied to serial transmission. [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to this bit after reading 1
[Clearing condition] * 5, 4 3 TEND All 0 0 R/(W)* Reserved These bits are always read as 0. Transmit End [Setting condition] * When the last bit of data is transmitted, the TDRE bit is 1 When 0 is written to this bit after reading 1 When data is written in SSTDR
[Clearing conditions] * *
Rev. 3.00 May 15, 2007 Page 291 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Bit 2
Bit Name TDRE
Initial Value 1
R/W R/(W)*
Description Transmit Data Empty [Setting conditions] * * When the TE bit in SSER is 0 When data transfer is performed from SSTDR to SSTRSR and data can be written in SSTDR When 0 is written to this bit after reading 1 When data is written in SSTDR
[Clearing conditions] * * 1 RDRF 0 R/(W)*
Receive Data Register Full [Setting condition] * When serial reception is completed normally and receive data is transferred from SSTRSR to SSRDR When 0 is written to this bit after reading 1 When data is read from SSRDR
[Clearing conditions] * * 0 CE 0 R/(W)*
Conflict Error Flag [Setting conditions] * * When serial communication is started while SSUMS = 1 and MSS =1, the SCS pin input is low When the SCS pin level changes from low to high during transfer while SSUMS = 1 and MSS = 0 When 0 is written to this bit after reading 1
[Clearing condition] * Note: * Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 292 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.3.6
SS Receive Data Register (SSRDR)
SSRDR is an 8-bit register that stores received serial data. When the SSU has received one byte of serial data, it transfers the received serial data from SSTRSR and the data is stored. After this, SSTRSR is receive-enabled. As SSTRSR and SSRDR function as a double buffer in this way, continuous receive operations are possible. SSRDR is a read-only register and cannot be written to by the CPU. SSRDR is initialized to H'00. 15.3.7 SS Transmit Data Register (SSTDR)
SSTDR is an 8-bit register that stores serial data for transmission. SSTDR can be read or written to by the CPU at all times. When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to SSTRSR and starts serial transmission. If the next transmit data has already been written to SSTDR during serial transmission, continuous serial transmission is possible. SSTDR is initialized to H'00. 15.3.8 SS Shift Register (SSTRSR)
SSTRSR is a shift register that transmits and receives serial data. When transmit data is transferred from SSTDR to SSTRSR, bit 0 in SSTDR is transferred to bit 0 in SSTRSR while the MLS bit in SSMR is 0 (LSB-first transfer) and bit 7 in SSTDR is transferred to bit 0 in SSTRSR while the MLS bit in SSMR is 1 (MSB-first transfer). SSTRSR cannot be directly accessed by the CPU.
15.4
15.4.1
Operation
Transfer Clock
Transfer clock can be selected from eight internal clocks and an external clock. When this module is used, the SSCK pin must be selected as a serial clock by setting the SCKS bit in SSCRH to 1. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is in the output state. If transfer is started, the SSCK pin outputs clocks of the transfer rate set in the CKS2 to CKS0 bits in SSMR. When the MSS bit is 0, an external clock is selected and the SSCK pin is in the input state.
Rev. 3.00 May 15, 2007 Page 293 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.2
Relationship between Clock Polarity and Phase, and Data
Relationship between clock polarity and phase, and transfer data changes according to a combination of the SSUMS bit in SSCRL and the CPOS and CPHS bits in SSMR. Figure 15.2 shows the relationship. MSB-first transfer or LSB first transfer can be selected by the setting of the MLS bit in SSMR. When the MLS bit is 0, transfer is started from LSB to MSB. When the MLS bit is 1, transfer is started from MSB to LSB.
(1) When CPHS = 0, CPOS =0, and SSUMS = 0: SSCK SSO, SSI Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
(2) When CPHS = 0 and SSUMS = 1: SSCK (CPOS = 0) SSCK (CPOS = 1) SSO, SSI SCS (3) When CPHS = 1 and SSUMS = 1: SSCK (CPOS = 0) SSCK (CPOS = 1) SSO, SSI SCS Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Figure 15.2 Relationship between Clock Polarity and Phase, and Data
Rev. 3.00 May 15, 2007 Page 294 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.3
Relationship between Data Input/Output and Shift Register
Relationship of connection between the data input/output pin and SSTRSR changes according to a combination of the MSS bit in SSCRH and the SSUMS bit in SSCRL. It also changes by the BIDE bit in SSCRH. Figure 15.3 shows the relationship.
(1) When SSUMS = 0:
(2) When SSUMS = 1, BIDE = 0, and MSS = 1:
Shift register (SSTRSR)
SSO
Shift register (SSTRSR)
SSO
SSI
SSI
(3) When SSUMS = 1, BIDE = 0, and MSS = 0:
(4) When SSUMS = 1 and BIDE = 1:
Shift register (SSTRSR)
SSO
Shift register (SSTRSR)
SSO
SSI
SSI
Figure 15.3 Relationship between Data Input/Output Pin and Shift Register
Rev. 3.00 May 15, 2007 Page 295 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.4
Communication Modes and Pin Functions
The SSU switches functions of the input/output pin in each communication mode according to the settings of the MSS bit in SSCRH and the RE and TE bits in SSER. Figure 15.2 shows the relationship between communication modes and the input/output pins. In bidirectional communication mode, neither TE nor RE should be set to 1. Table 15.2 Relationship between Communication Modes and Input/Output Pins
Communication Mode Clocked Synchronous Communication Mode Register State SSUMS 0 BIDE x MSS 0 TE 0 1 RE 1 0 1 1 0 1 1 0 1 Four-Line Bus Communication Mode 1 0 0 0 1 1 0 1 1 0 1 1 0 1 Four-Line Bus (Bidirectional) Communication Mode [Legend] 1 1 0 0 1 1 0 1 x: Don't care. : Can be used as a general I/O port. 1 0 1 0 SSI In In In In Out Out In In Pin State SSO Out Out Out Out In In Out Out In Out In Out SSCK In In In Out Out Out In In In Out Out Out In In Out Out
Rev. 3.00 May 15, 2007 Page 296 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.5
Operation in Clocked Synchronous Communication Mode
Initialization in Clocked Synchronous Communication Mode: Figure 15.4 shows the initialization in clocked synchronous communication mode. Before transmitting and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized. Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE bits in SSER to 0
Clear SSUMS bit in SSCRL to 0
Clear CPOS and CPHS bits to 0 and set MLS and CKS2 to CKS0 bits in SSMR Set SCKS bit in SSCRH to 1 and set MSS and SOOS bits
Clear ORER bit in SSSR to 0
Set the TE and RE bits in SSER to 1 and set RIE, TIE, TEIE, and RSSTP bits according to transmission/ reception/transmission and reception
End
Figure 15.4 Initialization in Clocked Synchronous Communication Mode
Rev. 3.00 May 15, 2007 Page 297 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Serial Data Transmission: Figure 15.5 shows an example of the SSU operation for transmission. In serial transmission, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, it outputs data in synchronized with the input clock. When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is generated. When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is fixed high. While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before transmission. Figure 15.6 shows a sample flowchart for serial data transmission.
SSCK
SSO
Bit 0
Bit 1 One frame
Bit 7
Bit 0
Bit 1 One frame
Bit 7
TDRE
TEND LSI Operation TXI generated TXI generated TEI generated
User processing
Write data in SSTDR
Write data in SSTDR
Figure 15.5 Example of Operation in Data Transmission
Rev. 3.00 May 15, 2007 Page 298 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Start
Initialization
[1]
Read TDRE bit in SSSR No TDRE = 1? Yes Write transmit data in SSTDR
[1] After reading SSSR and confirming that the TDRE bit is 1, write transmit data in SSTDR. Then the TDRE bit is automatically cleared to 0.
[2]
Data transmission continued?
Yes
[2] Determine whether data transmission is continued.
No [3] Read TEND bit in SSSR [3] Read 1 from the TEND bit in SSSR to confirm that data transmission is completed. After the TEND bit is set to 1, clear the TEND bit and TE bit in SSER to 0 and transmit mode is ended.
No TEND = 1? Yes Clear TEND bit and TE bit in SSER to 0
End
Figure 15.6 Sample Serial Transmission Flowchart
Rev. 3.00 May 15, 2007 Page 299 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Serial Data Reception: Figure 15.7 shows an example of the SSU operation for reception. In serial reception, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a slave device, it inputs data in synchronized with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts reception by performing dummy read on SSRDR. After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in SSRDR. If the RIE bit in SSER is set to 1 at this time, a RXI is generated. If SSRDR is read, the RDRF bit is automatically cleared to 0. When the SSU is set as a master device and reception is ended, received data is read after setting the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped. After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if SSRDR is read while the RE bit is set to 1, received clock is output again. When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1, reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before reception. Figure 15.8 shows a sample flowchart for serial data reception.
SSCK
SSO
Bit 0 One frame
Bit 7
Bit 0 One frame
Bit 7
Bit 0
Bit 7
RDRF
RSSTP LSI operation User processing Dummy read on SSRDR RXI generated RXI generated RXI generated
Read data in SSRDR
Set RSSTP to 1Read data in SSRDR
Figure 15.7 Example of Operation in Data Reception (MSS = 1)
Rev. 3.00 May 15, 2007 Page 300 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Start Initialization [1] Dummy read on SSRDR [1] After setting each register in the SSU, dummy read on SSRDR is performed and reception is started. Yes [2] Determine whether the last one byte of data is received. When the last one byte of data is received, set to stop reception after the data is received.
[2]
Last reception? No Read ORER
[3]
ORER = 1? No Read RDRF
Yes [3][6] When a receive error occurs, clear the ORER flag to 0 after the ORER flag in SSSR is read and an appropriate error processing is performed. When the ORER flag is set to 1, transmission/reception cannot be started again. [4] Confirm that the RDRF bit is 1. If the RDRF bit is 1, receive data in SSRDR is read. If the SSRDR bit is read, the RDRF bit is automatically cleared.
[4] No RDRF = 1? Yes Read receive data in SSRDR
[5]
Set RSSTP to 1
[5] Before the last one byte of data is received, set the RSSTP bit to 1 and reception is stopped after the data is received.
Read ORER Yes ORER = 1? No Read RDRF No [7] Yes RE = 0, RSSTP = 0 Read receive data in SSRDR RDRF = 1? [7] Confirm that the RDRF bit is 1. To end reception, clear the RE and RSSTP bits to 0 and then read the last receive data. If the Overrun error SSRDR bit is read before clearing the RE bit, processing reception is started again.
[6]
End
Figure 15.8 Sample Serial Reception Flowchart (MSS = 1)
Rev. 3.00 May 15, 2007 Page 301 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
Serial Data Transmission and Reception: Data transmission and reception is a combined operation of data transmission and reception which are described before. Transmission and reception is started by writing data in SSTDR. When the eighth clock rises or the ORER bit is set to 1 while the TDRE bit is set to 1, transmission and reception is stopped. To switch from transmit mode (TE = 1) or receive mode (RE = 1) to transmit and receive mode (TE = RE = 1), the TE and RE bits should be cleared to 0. After confirming that the TEND, RDRF, and ORER bits are cleared to 0, set the TE and RE bits to 1. Figure 15.9 shows a sample flowchart for serial transmit and receive operations.
Start
Initialization
[1]
Read TDRE in SSSR No TDRE = 1? Yes Write transmit data in SSTDR
[1] After reading SSSR and confirming that the TDRE bit is 1, write transmit data in SSTDR. Then the TDRE bit is automatically cleared to 0.
[2]
Read RDRF in SSSR
No
RDRF = 1? Yes Read receive data in SSRDR Yes
[2] Confirm that the RDRF bit is 1. If the RDRF bit is 1, receive data in SSRDR is read. If the SSRDR bit is read, the RDRF bit is automatically cleared.
[3]
Data transmission continued?
[3] Determine whether data transmission is continued.
No [4] Clear TEND to 0 and clear TE and RE in SSER to 0 [4] To end transmit and receive mode, clear the TEND bit to 0 and clear the TE and RE bits in SSER to 0.
End
Figure 15.9 Sample Flowchart for Serial Transmit and Receive Operations
Rev. 3.00 May 15, 2007 Page 302 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.6
Operation in Four-Line Bus Communication Mode
Four-line bus communication mode is a mode which communicates with the four-line bus; a clock line, a data input line, a data output line, and a chip select line. This mode includes bidirectional mode in which the data input line and the data output line function as a single pin. The data input line and the data output line are changed according to the settings of the MSS and BIDE bits in SSCRH. For details, refer to section 15.4.3, Relationship between Data Input/Output and Shift Register. In this mode, relationship between clock polarity and phase, and data can be set by the CPOS and CPHS bits in SSMR. For details, refer to section 15.4.2, Relationship between Clock Polarity and Phase, and Data. When the SSU is set as a master device, the chip select line controls output. When the SSU is set as a slave device, the chip select line controls input. When the SSU is set as a master device, the chip select line controls output of the SCS pin or controls output of a general port by setting the CSS1 bit in SSCRH to 1. When the SSU is set as a slave device, the chip select line sets the SCS pin as an input pin by setting the CSS1 and CSS0 bits in SSCRH to 01. In four-line bus communication mode, the MLS bit in SSMR is set to 1 and transfer is performed in MSB-first order.
Rev. 3.00 May 15, 2007 Page 303 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.7
Initialization in Four-Line Bus Communication Mode
Figure 15.10 shows the initialization in four-line bus communication mode. Before transmitting and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized. Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF and ORER flags, or the contents of SSRDR.
Start
Clear TE and RE in SSER to 0
Set SSUMS in SSCRL to 1
[1]
Set MLS in SSMR to 1 and set CPOS, CPHS, and CKS2 to CKS0
[1] The MLS bit is set to 1 for MSB-first transfer. The clock polarity and phase are set in the CPOS and CPHS bits.
[2]
Set SCKS in SSCRH to 1 and set BIDE, MSS, SOOS, CSS1, and CSS0
[2] In bidirectional mode, the BIDE bit is set to 1 and input/output of the SCS pin is set by the CSS1 and CSS0 bits.
Clear ORER in SSSR to 0
Set TE and RE in SSER to 1 and set RIE, TIE, TEIE, and RSSTP according to transmission/reception/ transmission and reception
End
Figure 15.10 Initialization in Four-Line Bus Communication Mode
Rev. 3.00 May 15, 2007 Page 304 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.8
Serial Data Transmission
Figure 15.11 shows an example of the SSU operation for transmission. In serial transmission, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, the SCS pin is in the low-input state and the SSU outputs data in synchronized with the input clock. When the SSU writes transmit data in SSTDR after setting the TE bit to 1, the TDRE flag is automatically cleared to 0 and data is transferred from SSTDR to SSTRSR. Then the SSU sets the TDRE flag to 1 and starts transmission. If the TIE bit in SSER is set to 1 at this time, a TXI is generated. When the TDRE flag is 0 and one frame of data has transferred, data is transferred from SSTDR to SSTRSR and serial transmission of the next frame is started. If the eighth bit is transmitted while the TDRE flag is 1, the TEND bit in SSSR is set to 1 and the state is retained. If the TEIE bit in SSER is set to 1 at this time, a TEI is generated. After transmission is ended, the SSCK pin is fixed high and the SCS pin goes high. When continuous transmission is performed with the SCS pin low, the next data should be written to SSTDR before transmitting the eighth bit of the frame. While the ORER bit in SSSR is set to 1, transmission cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before transmission. The difference between this mode and clocked synchronous communication mode is as follows: when the SSU is set as a master device, the SSO pin is in the Hi-Z state if the SCS pin is in the HiZ state and when the SSU is set as a slave device, the SSI pin is in the Hi-Z state if the SCS pin is in the high-input state. The sample flowchart for serial data transmission is the same as that in clocked synchronous communication mode.
Rev. 3.00 May 15, 2007 Page 305 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
(1) When CPOS = 0 and CPHS = 0: SCS (output) SSCK (Hi-Z)
SSO
Bit 7
Bit 6 One frame
Bit 0
Bit 7
Bit 6 One frame
Bit 0
TDRE
TEND LSI operation User processing TXI generated Write data in SSTDR Write data in SSTDR TXI generated TEI generated
(2) When CPOS = 0 and CPHS = 1: SCS (output) SSCK (Hi-Z)
SSO
Bit 7
Bit 6 One frame
Bit 0
Bit 7
Bit 6 One frame
Bit 0
TDRE
TEND LSI operation User processing TXI generated Write data in SSTDR Write data in SSTDR TXI generated TEI generated
Figure 15.11 Example of Operation in Data Transmission (MSS = 1)
Rev. 3.00 May 15, 2007 Page 306 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.9
Serial Data Reception
Figure 15.12 shows an example of the SSU operation for reception. In serial reception, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a slave device, the SCS pin is in the low-input state and inputs data in synchronized with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts reception by performing dummy read on SSRDR. After eight bits of data is received, the RDRF bit in SSSR is set to 1 and received data is stored in SSRDR. If the RIE bit in SSER is set to 1 at this time, an RXI is generated. If SSRDR is read, the RDRF bit is automatically cleared to 0. When the SSU is set as a master device and reception is ended, received data is read after setting the RSSTP bit in SSER to 1. Then the SSU outputs eight bits of clocks and operation is stopped. After that, the RE and RSSTP bits are cleared to 0 and the last received data is read. Note that if SSRDR is read while the RE bit is set to 1, received clock is output again. When the eighth clock rises while the RDRF bit is 1, the ORER bit in SSSR is set. Then an overrun error (OEI) is generated and operation is stopped. When the ORER bit in SSSR is set to 1, reception cannot be performed. Therefore confirm that the ORER bit is cleared to 0 before reception. The set timings of the RDRF and ORER flags differ according to the CPHS setting. These timings are shown in figure 15.12. When the CPHS bit is set to 1, the flag is set during the frame. Therefore care should be taken at the end of reception. The sample flowchart for serial data reception is the same as that in clocked synchronous communication mode.
Rev. 3.00 May 15, 2007 Page 307 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
(1) When CPOS = 0 and CPHS = 0: SCS (output) SSCK (Hi-Z)
SSI
Bit 7 One frame
Bit 0
Bit 7 One frame
Bit 0
Bit 7
Bit 0
RDRF
RSSTP LSI operation User processing Dummy read on SSRDR RXI generated RXI generated RXI generated
Read data in SSRDR
Set RSSTP to 1Read data in SSRDR
(2) When CPOS = 0 and CPHS = 1: SCS (output) SSCK (Hi-Z)
SSI
Bit 7 One frame
Bit 0
Bit 7 One frame
Bit 0
Bit 7
Bit 0
RDRF
RSSTP LSI operation User processing RXI generated Dummy read on SSRDR RXI generated Read data in SSRDR RXI generated
Set RSSTP to 1Read data in SSRDR
Figure 15.12 Example of Operation in Data Reception (MSS = 1)
Rev. 3.00 May 15, 2007 Page 308 of 516 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.10 SCS Pin Control and Arbitration When the SSUMS bit in SSCRL is set to 1 and the CSS1 bit in SSCRH is set to 1, the MSS bit in SSCRH is set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer. If the SSU detects that the synchronized internal SCS pin goes low in this period, the CE bit in SSSR is set and the MSS bit is cleared. Note: When a conflict error is set, subsequent transmit operation is not possible. Therefore the CE bit must be cleared to 0 before starting transmission. When the multimaster error is used, the CSOS bit in SSCRL should be set to 1.
SCS input Internal SCS (synchronized)
MSS
Transfer start
Write data in SSTDR
CE (Hi-Z)
SCS output
Maximum time of SCS internal synchronization Arbitration detection period
Figure 15.13 Arbitration Check Timing
Rev. 3.00 May 15, 2007 Page 309 of 518 REJ09B0152-0300
Section 15 Synchronous Serial Communication Unit (SSU)
15.4.11 Interrupt Requests The SSU has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the common vector address, interrupt sources must be determined by flags. Table 15.3 lists the interrupt requests. Table 15.3 Interrupt Requests
Interrupt Request Transmit data empty Transmit end Receive data full Overrun error Conflict error Abbreviation TXI TEI RXI OEI CEI Interrupt Condition (TIE = 1), (TDRE = 1) (TEIE = 1), (TEND = 1) (RIE = 1), (RDRF = 1) (RIE = 1), (ORER = 1) (CEIE = 1), (CE = 1)
When an interrupt condition shown in table 15.3 is 1 and the I bit in CCR is 0, the CPU executes the interrupt exception handling. Each interrupt source must be cleared during the exception handling. Note that the TDRE and TEND bits are automatically cleared by writing transmit data in SSTDR and the RDRF bit is automatically cleared by reading SSRDR. When transmit data is written in SSTDR, the TDRE bit is set again at the same time. Then if the TDRE bit is cleared, additional one byte of data may be transmitted.
15.5
Usage Note
When writing 1 to the SOLP bit in SSCRH (to enable write protect) after writing 0 to it (to disable write protect), the SOL bit may be changed without being protected. To avoid this, before writing 1 to the SOLP bit (to enable write protect), write the current value of the SOL bit to itself. With this procedure, the write protect can be performed on the SOL bit.
Rev. 3.00 May 15, 2007 Page 310 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Section 16 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The configuration of the registers that control the I2C bus differs partly from the Philips configuration, however. Figure 16.1 shows a block diagram of the I2C bus interface 2. Figure 16.2 shows an example of I/O pin connections to external circuits.
16.1
Features
* Selection of I2C format or clock synchronous serial format * Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (The IIC2 is halted as the initial value. For details, refer to section 5.4, Module Standby Function.) I2C bus format Start and stop conditions generated automatically in master mode Selection of acknowledge output levels when receiving Automatic loading of acknowledge bit when transmitting Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission/reception is not yet possible, set the SCL to low until preparations are completed. * Six interrupt sources Transmit data empty (including slave-address match), transmit end, receive data full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, SCL and SDA pins, function as CMOS outputs in normal operation (when the port/serial function is selected) and NMOS outputs when the bus drive function is selected. Clock synchronous format * Four interrupt sources Transmit-data-empty, transmit-end, receive-data-full, and overrun error
Rev. 3.00 May 15, 2007 Page 311 of 516 REJ09B0152-0300
* * * *
Section 16 I C Bus Interface 2 (IIC2)
2
Transfer clock generation circuit
SCL
Output control
Transmission/ reception control circuit
ICCR1 ICCR2 ICMR
Noise canceler ICDRT SAR
SDA
Output control
ICDRS
Noise canceler
Address comparator ICDRR Bus state decision circuit Arbitration decision circuit
ICSR ICIER Interrupt generator Interrupt request
[Legend] ICCR1 : I2C bus control register 1 ICCR2 : I2C bus control register 2 ICMR : I2C bus mode register ICSR : I2C bus status register ICIER : I2C bus interrupt enable register ICDRT : I2C bus transmit data register ICDRR : I2C bus receive data register ICDRS : I2C bus shift register SAR : Slave address register
Figure 16.1 Block Diagram of I2C Bus Interface 2
Rev. 3.00 May 15, 2007 Page 312 of 516 REJ09B0152-0300
Internal data bus
Section 16 I C Bus Interface 2 (IIC2)
2
Vcc
Vcc
SCL in SCL out
SCL
SCL
SDA in SDA out
SDA
SDA
SCL SDA
(Master)
SCL in SCL out
SCL in SCL out
SDA in SDA out (Slave 1)
SDA in SDA out (Slave 2)
Figure 16.2 External Circuit Connections of I/O Pins
16.2
Input/Output Pins
Table 16.1 shows the pin configuration of the I2C bus interface 2. Table 16.1 Pin Configuration
Name Serial clock pin Serial data pin Abbreviation SCL SDA I/O I/O I/O Function IIC serial clock input/output IIC serial data input/output
Rev. 3.00 May 15, 2007 Page 313 of 516 REJ09B0152-0300
SCL SDA
Section 16 I C Bus Interface 2 (IIC2)
2
16.3
Register Descriptions
The I2C bus interface 2 has the following registers. * * * * * * * * * I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) Slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) I2C Bus Control Register 1 (ICCR1)
16.3.1
ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit 7 Bit Name ICE Initial Value 0 R/W R/W Description I2C Bus Interface Enable 0: This module is halted. (SCL and SDA pins are set to the port/serial function.) 1: This bit is enabled for transfer operations. (SCL and SDA pins are bus drive state.) 6 RCVD 0 R/W Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception
Rev. 3.00 May 15, 2007 Page 314 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Bit 5 4
Bit Name MST TRS
Initial Value 0 0
R/W R/W R/W
Description Master/Slave Select Transmit/Receive Select In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. After data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to SAR and the eighth bit is 1, TRS is automatically set to 1. If an overrun error occurs in master mode with the clock synchronous serial format, MST is cleared to 0 and slave receive mode is entered. Operating modes are described below according to MST and TRS combination. When clock synchronous serial format is selected and MST is 1, clock is output. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode
2
3 2 1 0
CKS3 CKS2 CKS1 CKS0
0 0 0 0
R/W R/W R/W R/W
Transfer Clock Select 3 to 0 These bits are valid only in master mode and should be set according to the necessary transfer rate (refer to table 16.2). These bit are used to specify the data setup time in slave transmit mode. The data setup time is secured for 10tcyc when CKS3 = 0 and for 20tcyc when CKS3 = 1.
Rev. 3.00 May 15, 2007 Page 315 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Table 16.2 Transfer Rate
Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 1 1 0 1 1 0 0 1 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 2 MHz 71.4 kHz 50.0 kHz 41.7 kHz 31.3 kHz 25.0 kHz 20.0 kHz 17.9 kHz 15.6 kHz 35.7 kHz 25.0 kHz 20.8 kHz 15.6 kHz 12.5 kHz 10.0 kHz 8.9 kHz 7.8 kHz Transfer Rate = 5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz
Rev. 3.00 May 15, 2007 Page 316 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.3.2
I2C Bus Control Register 2 (ICCR2)
ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2.
Bit 7 Bit Name BBSY Initial Value 0 R/W R/W Description Bus Busy This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clock synchronous serial 2 format, this bit has no meaning. With the I C bus format, this bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. Write 1 to BBSY and 0 to SCP to issue a start condition. Follow this procedure when also re-transmitting a start condition. Write 0 in BBSY and 0 in SCP to issue a stop condition. To issue start/stop conditions, use the MOV instruction. 6 SCP 1 R/W Start/Stop Issue Condition Disable The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A repeated start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. 5 SDAO 1 R/W SDA Output Value Control This bit is used with SDAOP when modifying output level of SDA. This bit should not be manipulated during transfer. 0: When reading, SDA pin outputs low. When writing, SDA pin is changed to output low. 1: When reading, SDA pin outputs high. When writing, SDA pin is changed to output Hi-Z (outputs high by external pull-up resistance).
2
Rev. 3.00 May 15, 2007 Page 317 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name SDAOP
Initial Value 1
R/W R/W
Description SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1.
3
SCLO
1
R
This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low. Reserved This bit is always read as 1, and cannot be modified. IIC Control Part Reset This bit resets the control part except for I C registers. If this bit is set to 1 when hang-up occurs because of 2 2 communication failure during I C operation, I C control part can be reset without setting ports and initializing registers.
2
2 1
IICRST
1 0
R/W
0
1
Reserved This bit is always read as 1, and cannot be modified.
Rev. 3.00 May 15, 2007 Page 318 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.3.3
I2C Bus Mode Register (ICMR)
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count.
Bit 7 Bit Name MLS Initial Value 0 R/W R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I2C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit In master mode with the I C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The setting of this bit is invalid in slave mode with the 2 I C bus format or with the clock synchronous serial format. 5, 4 All 1 Reserved These bits are always read as 1, and cannot be modified. 3 BCWP 1 R/W BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read. When writing, settings of BC2 to BC0 are invalid.
2
Rev. 3.00 May 15, 2007 Page 319 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Bit 2 1 0
Bit Name BC2 BC1 BC0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. With the I2C bus format, the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL pin is low. The value returns to 000 at the end of a data transfer, including the acknowledge bit. With the clock synchronous serial format, these bits should not be modified. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits
2
Clock Synchronous Serial Format 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits
Rev. 3.00 May 15, 2007 Page 320 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.3.4
I2C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received.
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled. 1: Transmit data empty interrupt request (TXI) is enabled. 6 TEIE 0 R/W Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled. 1: Transmit end interrupt request (TEI) is enabled. 5 RIE 0 R/W Receive Interrupt Enable This bit enables or disables the receive data full interrupt request (RXI) and the overrun error interrupt request (ERI) with the clock synchronous format, when a receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clock synchronous format are disabled. 1: Receive data full interrupt request (RXI) and overrun error interrupt request (ERI) with the clock synchronous format are enabled.
Rev. 3.00 May 15, 2007 Page 321 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name NAKIE
Initial Value 0
R/W R/W
Description NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clock synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.
3
STIE
0
R/W
Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgment Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted.
1
ACKBR
0
R
Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing.
Rev. 3.00 May 15, 2007 Page 322 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.3.5
I2C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit 7 Bit Name TDRE Initial Value 0 R/W Description
R/(W)* Transmit Data Register Empty [Setting conditions] * * * * When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When TRS is set When a start condition (including re-transfer) has been issued When transmit mode is entered from receive mode in slave mode When 0 is written in TDRE after reading TDRE = 1 When data is written to ICDRT with an instruction
[Clearing conditions] * * 6 TEND 0
R/(W)* Transmit End [Setting conditions] * * When the ninth clock of SCL rises with the I C bus format while the TDRE flag is 1 When the final bit of transmit frame is sent with the clock synchronous serial format When 0 is written in TEND after reading TEND = 1 When data is written to ICDRT with an instruction
2
[Clearing conditions] * * 5 RDRF 0
R/(W)* Receive Data Register Full [Setting condition] * When a receive data is transferred from ICDRS to ICDRR When 0 is written in RDRF after reading RDRF = 1 When ICDRR is read with an instruction
[Clearing conditions] * *
Rev. 3.00 May 15, 2007 Page 323 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Bit 4
Bit Name NACKF
Initial Value 0
R/W
Description
R/(W)* No Acknowledge Detection Flag [Setting condition] * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 When 0 is written in NACKF after reading NACKF = 1
[Clearing condition] * 3 STOP 0
R/(W)* Stop Condition Detection Flag [Setting conditions] * * In master mode, when a stop condition is detected after the completion of frame transfer In slave mode, when a stop condition is detected, after the slave address of the first byte, following the general call and the detection of the start condition, matches the address set in SAR When 0 is written in STOP after reading STOP = 1
[Clearing condition] *
Rev. 3.00 May 15, 2007 Page 324 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Bit 2
Bit Name AL/OVE
Initial Value 0
R/W
Description
R/(W)* Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master 2 mode with the I C bus format and that the final bit has been received while RDRF = 1 with the clock synchronous format. When two or more master devices attempt to seize the 2 bus at nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode When the SDA pin outputs high in master mode while a start condition is detected When the final bit is received with the clock synchronous format while RDRF = 1 When 0 is written in AL/OVE after reading AL/OVE =1
[Clearing condition] * 1 AAS 0
R/(W)* Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] * * When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode. When 0 is written in AAS after reading AAS = 1
[Clearing condition] *
Rev. 3.00 May 15, 2007 Page 325 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Bit 0
Bit Name ADZ
Initial Value 0
R/W
Description
2
R/(W)* General Call Address Recognition Flag This bit is valid in I C bus format slave receive mode. [Setting condition] * When the general call address is detected in slave receive mode When 0 is written in ADZ after reading ADZ = 1
[Clearing condition] * Note: * Only 0 can be written to clear the flag.
16.3.6
Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
Bit 7 to 1 Bit Name SVA6 to SVA0 Initial Value All 0 R/W R/W Description Slave Address 6 to 0 These bits set a unique address in bits SVA6 to SVA0, differing form the addresses of other slave devices 2 connected to the I C bus. 0 R/W Format Select 0: I C bus format is selected. 1: Clock synchronous serial format is selected.
2
0
FS
16.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1 and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of ICDRT is H'FF. The initial value of ICDRT is H'FF.
Rev. 3.00 May 15, 2007 Page 326 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.3.8
I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR is H'FF. 16.3.9 I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the CPU.
Rev. 3.00 May 15, 2007 Page 327 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.4
Operation
The I2C bus interface 2 can communicate either in I2C bus mode or clock synchronous serial mode by setting FS in SAR. 16.4.1 I2C Bus Format
Figure 16.3 shows the I2C bus formats. Figure 16.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
(a) I2C bus format (FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1)
(b) I2C bus format (Repeated start condition, FS = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1)
Figure 16.3 I2C Bus Formats
SDA SCL S 1-7 SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A P
Figure 16.4 I2C Bus Timing [Legend] S: SLA: R/W: Start condition. The master device drives SDA from high to low while SCL is high. Slave address Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high.
Rev. 3.00 May 15, 2007 Page 328 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.4.2
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For master transmit mode operation timing, refer to figures 16.5 and 16.6. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV instruction. (Start condition issued) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0, and data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue the stop condition. To issue the stop condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
Rev. 3.00 May 15, 2007 Page 329 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output)
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0 R/W
9
1 Bit 7
2 Bit 6
Slave address
SDA (Slave output)
A
TDRE
TEND
ICDRT
Address + R/W
Data 1
Data 2
ICDRS
Address + R/W
Data 1
User processing
[2] Instruction of start condition issuance [3] Write data to ICDRT (first byte)
[4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte)
Figure 16.5 Master Transmit Mode Operation Timing (1)
SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A
9
1 Bit 7
2 Bit 6
3 Bit 5
4 Bit 4
5 Bit 3
6 Bit 2
7 Bit 1
8 Bit 0
9
A/A
TEND
ICDRT
Data n
ICDRS
Data n
User [5] Write data to ICDRT processing
[6] Issue stop condition. Clear TEND. [7] Set slave receive mode
Figure 16.6 Master Transmit Mode Operation Timing (2)
Rev. 3.00 May 15, 2007 Page 330 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 16.7 and 16.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. The master device outputs the level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse. 3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF is cleared to 0. 4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is fixed low until ICDRR is read. 5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition. 7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode.
Rev. 3.00 May 15, 2007 Page 331 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A 9 1
Master receive mode 2 3 4 5 6 7 8 9 A 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR User processing
Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read)
Figure 16.7 Master Receive Mode Operation Timing (1)
Rev. 3.00 May 15, 2007 Page 332 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output) SDA (Slave output)
9 A
1
2
3
4
5
6
7
8
9 A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDRF
RCVD
ICDRS Data n-1
Data n
ICDRR User processing
Data n-1
Data n
[5] Read ICDRR after setting RCVD
[7] Read ICDRR, and clear RCVD
[6] Issue stop condition
[8] Set slave receive mode
Figure 16.8 Master Receive Mode Operation Timing (2) 16.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 16.9 and 16.10. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free. 5. Clear TDRE.
Rev. 3.00 May 15, 2007 Page 333 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Slave receive mode
SCL (Master output) SDA (Master output) SCL (Slave output)
Slave transmit mode 9 1 2 3 4 5 6 7 8 9 A 1
SDA (Slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
ICDRT
Data 1
Data 2
Data 3
ICDRS
Data 1
Data 2
ICDRR User processing
[2] Write data to ICDRT (data 1)
[2] Write data to ICDRT (data 2)
[2] Write data to ICDRT (data 3)
Figure 16.9 Slave Transmit Mode Operation Timing (1)
Rev. 3.00 May 15, 2007 Page 334 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Slave receive mode Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
TDRE 9 A 1 2 3 4 5 6 7 8 9 A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TEND TRS
ICDRT
ICDRS
Data n
ICDRR
User processing
[3] Clear TEND
[4] Read ICDRR (dummy read) after clearing TRS
[5] Clear TDRE
Figure 16.10 Slave Transmit Mode Operation Timing (2)
Rev. 3.00 May 15, 2007 Page 335 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.4.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, refer to figures 16.11 and 16.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data show the slave address and R/W, it is not used.) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR.
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
2
3
4
5
6
7
8
9
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User processing
Data 1
[2] Read ICDRR (dummy read)
[2] Read ICDRR
Figure 16.11 Slave Receive Mode Operation Timing (1)
Rev. 3.00 May 15, 2007 Page 336 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
Bit 7
2
Bit 6
3
Bit 5
4
Bit 4
5
Bit 3
6
Bit 2
7
Bit 1
8
Bit 0
9
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User processing
Data 1
[3] Set ACKBT
[3] Read ICDRR [4] Read ICDRR
Figure 16.12 Slave Receive Mode Operation Timing (2) 16.4.6 Clock Synchronous Serial Format
This module can be operated with the clock synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. (1) Data Transfer Format
Figure 16.13 shows the clock synchronous serial transfer format. The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the SDAO bit in ICCR2.
SCL
SDA
Bit 0
Bit 1
Bit 2 Bit 3 Bit 4
Bit 5 Bit 6
Bit 7
Figure 16.13 Clock Synchronous Serial Transfer Format
Rev. 3.00 May 15, 2007 Page 337 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
(2)
Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For transmit mode operation timing, refer to figure 16.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set. 3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous transmission is performed by writing data to ICDRT every time TDRE is set. When changing from transmit mode to receive mode, clear TRS while TDRE is 1.
SCL SDA (Output) TRS TDRE ICDRT ICDRS
1
2
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
Bit 0
Bit 1
Data 1 Data 1
Data 2 Data 2
Data 3 Data 3
User processing
[3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS
[3] Write data to ICDRT
[3] Write data to ICDRT
Figure 16.14 Transmit Mode Operation Timing
Rev. 3.00 May 15, 2007 Page 338 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
(3)
Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to figure 16.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial setting) 2. When the transfer clock is output, set MST to 1 to start outputting the receive clock. 3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is continually output. The continuous reception is performed by reading ICDRR every time RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR. 4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is fixed high after receiving the next byte data.
SCL SDA (Input) MST TRS
1
2
7 Bit 6
8 Bit 7
1 Bit 0
7 Bit 6
8 Bit 7
1 Bit 0
2 Bit 1
Bit 0
Bit 1
RDRF ICDRS ICDRR Data 1 Data 2 Data 3
Data 1 [2] Set MST (when outputting the clock)
Data 2
User processing
[3] Read ICDRR
[3] Read ICDRR
Figure 16.15 Receive Mode Operation Timing
Rev. 3.00 May 15, 2007 Page 339 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.4.7
Noise Canceler
The logic levels on the SCL and SDA pins are internally latched via noise cancelers. Figure 16.16 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C SCL or SDA input signal D Latch Q D
C Q Latch Match detector Internal SCL or SDA signal
System clock period Sampling clock
Figure 16.16 Block Diagram of Noise Conceler 16.4.8 Example of Use
Flowcharts in respective modes that use the I2C bus interface 2 are shown in figures 16.17 to 16.20.
Rev. 3.00 May 15, 2007 Page 340 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Start Initialize Read BBSY in ICCR2 No [1] BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1. Write 1 to BBSY and 0 to SCP. Write transmit data in ICDRT Read TEND in ICSR No [5] TEND=1 ? Yes Read ACKBR in ICIER ACKBR=0 ? Yes Transmit mode? Yes No Mater receive mode No [6] [9] Set the last byte of transmit data. [8] Wait for ICDRT empty. [3] [4] [5] [6] [4] [7] Set the second and subsequent bytes (except for the final byte) of transmit data. Issue the start condition. Set the first byte (slave address + R/W) of transmit data. Wait for 1 byte to be transmitted. Test the acknowledge transferred from the specified slave device. [1] [2] Test the status of the SCL and SDA lines. Set master transmit mode.
[2] [3]
[10] Wait for last byte to be transmitted. [11] Clear the TEND flag.
Write transmit data in ICDRT Read TDRE in ICSR No
[7] [12] Clear STOP flag. [13] Issue the stop condition. [14] Wait for the creation of stop condition. [15] Set slave receive mode. Clear TDRE. [9]
[8] TDRE=1 ? Yes
No
Last byte? Yes
Write transmit data in ICDRT Read TEND in ICSR No [10] TEND=1 ? Yes Clear TEND in ICSR Clear STOP in ISCR Write 0 to BBSY and SCP Read STOP in ICSR No [14] STOP=1 ? Yes Set MST to 0 and TRS to 0 in ICCR1 Clear TDRE in ICSR End [11] [12] [13]
[15]
Figure 16.17 Sample Flowchart for Master Transmit Mode
Rev. 3.00 May 15, 2007 Page 341 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Master receive mode [1] Clear TEND in ICSR Clear TRS in ICCR1 to 0 Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR No RDRF = 1 ? Yes Last receive - 1? No Read ICDRR Yes
[5] [4] [2]
Clear TEND, select master receive mode, and then clear TDRE.* Set acknowledge to the transmit device.* Dummy-read ICDDR.* Wait for 1 byte to be received Check whether it is the (last receive - 1). Read the receive data last. Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). Read the (final byte - 1) of receive data. Wait for the last byte to be receive.
[2]
[1]
[3] [4] [5] [6] [7] [8] [9]
[3]
[10] Clear STOP flag.
[6]
[11] Issue the stop condition. [12] Wait for the creation of stop condition. Set ACKBT in ICIER to 1
[7]
[13] Read the last byte of receive data. [14] Clear RCVD.
Set RCVD in ICCR1 to 1 Read ICDRR Read RDRF in ICSR No RDRF = 1? Yes Clear STOP in ICSR Write 0 to BBSY and SCP Read STOP in ICSR No
[12] [9] [8]
[15] Set slave receive mode.
[10] [11]
STOP = 1? Yes Read ICDRR
[13] [14]
Clear RCVD in ICCR1 to 0
Note: * Do not activate an interrupt during the execution of steps [1] to [3]. Clear MST in ICCR1 to 0 End
[15]
For single-byte reception, skip steps [2] to [6] after step [1]. Then, jump to step [7]. Dummy-read in step [8].
Figure 16.18 Sample Flowchart for Master Receive Mode
Rev. 3.00 May 15, 2007 Page 342 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Slave transmit mode Clear AAS in ICSR Write transmit data in ICDRT Read TDRE in ICSR No [3] TDRE=1 ? Yes No
Last byte?
[1] Clear the AAS flag. [1] [2] Set transmit data for ICDRT (except for the last data). [3] Wait for ICDRT empty. [2] [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. [6] Clear the TEND flag . [7] Set slave receive mode. [8] Dummy-read ICDRR to release the SCL line. [4] [9] Clear the TDRE flag.
Yes Write transmit data in ICDRT Read TEND in ICSR No
[5] TEND=1 ? Yes Clear TEND in ICSR Clear TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End
[6] [7] [8] [9]
Figure 16.19 Sample Flowchart for Slave Transmit Mode
Rev. 3.00 May 15, 2007 Page 343 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
Slave receive mode
[1] Clear the AAS flag.
Clear AAS in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR
[1] [2] Set acknowledge to the transmit device. [2] [3] Dummy-read ICDRR. [3] [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). [4] [6] Read the receive data. [7] Set acknowledge of the last byte.
Read RDRF in ICSR No RDRF = 1? Yes
Last receive - 1?
Yes
[5]
[8] Read the (last byte - 1) of receive data. [9] Wait the last byte to be received.
No Read ICDRR
[6] [10] Read for the last byte of receive data.
Set ACKBT in ICIER to 1
[7]
Read ICDRR Read RDRF in ICSR No
[8]
[9]
RDRF = 1? Yes Read ICDRR End
[10] For single-byte reception, skip steps [2] to [6] after step [1]. Then, jump to step [7]. Dummy-read in step [8].
Figure 16.20 Sample Flowchart for Slave Receive Mode
Rev. 3.00 May 15, 2007 Page 344 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.5
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun. Table 16.3 shows the contents of each interrupt request. Table 16.3 Interrupt Requests
Clock Synchronous Mode
Interrupt Request Transmit Data Empty Transmit End Receive Data Full STOP Recognition NACK Receive Arbitration Lost/Overrun
Abbreviation TXI TEI RXI STPI NAKI
Interrupt Condition (TDRE = 1) * (TIE = 1) (TEND = 1) * (TEIE = 1) (RDRF = 1) * (RIE = 1) (STOP = 1) * (STIE = 1) {(NACKF = 1) + (AL = 1)} * (NAKIE = 1)
I2C Mode
x x
When interrupt conditions described in table 16.3 are 1 and the I bit in CCR is 0, the CPU executes interrupt exception processing. Interrupt sources should be cleared in the exception processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive data of one byte may be transmitted.
Rev. 3.00 May 15, 2007 Page 345 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.6
Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states described below. * When SCL is driven to low by the slave device * When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 16.21 shows the timing of the bit synchronous circuit and table 16.4 shows the time when SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor timing reference clock
SCL
VIH
Internal SCL
Figure 16.21 Timing of Bit Synchronous Circuit Table 16.4 Time for Monitoring SCL
CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc
Rev. 3.00 May 15, 2007 Page 346 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.7
16.7.1
Usage Notes
Note on Issuing Stop Condition and Start (Re-Transmit) Condition
The stop condition or start (re-transmit) condition should be issued after recognizing the falling edge of the ninth clock. The falling edge of the ninth clock can be recognized by checking the SCLO bit in the I2C control register 2 (ICCR2). Note that if the stop condition or start (retransmit) condition is issued in a particular timing and the situations shown below, these conditions may not correctly output. 1. The rising edge of the SCL becomes less sharp and longer due to the SCL bus load (load capacitor and pull-up resistor) than the period defined in section 16.6, Bit Synchronous Circuit. 2. When the slave device elongates the low level period between the eighth and ninth clocks and activates the bit synchronous circuit. 16.7.2 Note on Setting WAIT Bit in I2C Bus Mode Register (ICMR)
The WAIT bit in the I2C bus mode register (ICMR) should be set to 0. Note that if the WAIT bit is set to 1, when a slave device holds the SCL signal low more than one transfer clock cycle during the eighth clock, the high level period of the ninth clock may be shorter than a given period. 16.7.3 Restriction on Transfer Rate Setting in Multimaster Operation
In multimaster operation, if the IIC transfer rate setting in this LSI is slower than those of the other masters, SCL may be output with an unexpected width. To avoid this phenomenon, set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest transfer rate of the other masters is set to 400 kbps, the IIC transfer rate in this LSI should be set to 223 kbps (= 400/1.18) or more.
Rev. 3.00 May 15, 2007 Page 347 of 516 REJ09B0152-0300
Section 16 I C Bus Interface 2 (IIC2)
2
16.7.4
Restriction on the Use of Bit Manipulation Instructions for MST and TRS Setting in Multimaster Operation
In multimaster operation, if the master transmit is set with bit manipulation instructions in the order from the MST bit to the TRS bit, the AL bit in the ICSR register will be set to 1 but the master transmit mode (MST = 1, TRS = 1) may be set, depending on the arbitration lost timing. To avoid this phenomenon, the following actions should be performed: * In multimaster operation, use the MOV instruction to set bits MST and TRS. * When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than MST = 0 and TRS = 0, set MST = 0 and TRS = 0 again.
16.7.5
Usage Note on Master Receive Mode
In master receive mode, SCL is fixed low on the falling edge of the 8th clock while the RDRF bit is set to 1. When ICDRR is read around the falling edge of the 8th clock, the clock is only fixed low in the 8th clock of the next round of data reception. The SCL is then released from its fixed state without reading ICDRR and the 9th clock is output. As a result, some receive data is lost. To avoid this phenomenon, the following actions should be performed: * Read ICDRR in master receive mode before the rising edge of the 8th clock. * Set RCVD to 1 in master receive mode and perform communication in units of one byte.
Rev. 3.00 May 15, 2007 Page 348 of 516 REJ09B0152-0300
Section 17 A/D Converter
Section 17 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to six analog input channels to be selected. The block diagram of the A/D converter is shown in figure 17.1.
17.1
* * * * *
Features
10-bit resolution Six input channels High-speed conversion: 12.4 s per channel (at 10-MHz operation) Sample and hold function Conversion start method A/D conversion can be started by software and external trigger. * Interrupt source An A/D conversion end interrupt request can be generated. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (The A/D converter is halted as the initial value. For details, refer to section 5.4, Module Standby Function.)
ADTRG AMR AN0 AN1 AN2 AN3 AN4 AN5 Multiplexer AVcc + Reference voltage VSS [Legend] AMR: ADSR: ADRR: IRRAD: A/D mode register A/D start register A/D result register A/D conversion end interrupt request flag Vss ADRR Comparator Control logic ADSR
AVCC
Internal data bus
IRRAD
Figure 17.1 Block Diagram of A/D Converter
ADCMS3AA_000020020900
Rev. 3.00 May 15, 2007 Page 349 of 516 REJ09B0152-0300
Section 17 A/D Converter
17.2
Input/Output Pins
Table 17.1 shows the pin configuration of the A/D converter. Table 17.1 Pin Configuration
Pin Name Analog power supply pin Ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 External trigger input pin Abbreviation AVcc Vss AN0 AN1 AN2 AN3 AN4 AN5 ADTRG I/O Input Input Input Input Input Input Input Input Input External trigger input that controls the A/D conversion start. Function Power supply and reference voltage of analog part Ground and reference voltage Analog input pins
17.3
Register Descriptions
The A/D converter has the following registers. * A/D result register (ADRR) * A/D mode register (AMR) * A/D start register (ADSR) 17.3.1 A/D Result Register (ADRR)
ADRR is a 16-bit read-only register that stores the results of A/D conversion. The data is stored in the upper 10 bits of ADRR. ADRR can be read by the CPU at any time, but the ADRR value during A/D conversion is undefined. After A/D conversion is completed, the conversion result is stored as 10-bit data, and this data is retained until the next conversion operation starts. The initial value of ADRR is undefined. This register must be read in words.
Rev. 3.00 May 15, 2007 Page 350 of 516 REJ09B0152-0300
Section 17 A/D Converter
17.3.2
A/D Mode Register (AMR)
AMR sets the A/D conversion time, and selects the external trigger and analog input pins.
Bit 7 6 Bit Name TRGE Initial Value 0 0 R/W R/W Description Reserved This bit is always read as 0 and cannot be modified. External Trigger Select Enables or disables the A/D conversion start by the external trigger input. 0: Disables the A/D conversion start by the external trigger input. 1: Starts A/D conversion at the rising or falling edge of the ADTRG pin The edge of the ADTRG pin is selected by the ADTRGNEG bit in IEGR. 5 4 CKS1 CKS0 0 0 R/W R/W Clock Select Select the A/D conversion clock source. 00: /8 (conversion time = 124 states (max.) (reference clock = ) 01: /4 (conversion time = 62 states (max.) (reference clock = ) 10: /2 (conversion time = 31 states (max.) (reference clock = ) 11: w/2 (conversion time = 31 states (max.) (reference clock = SUB) While CKS1 and CKS0 are all 1 in subactive or subsleep mode, the A/D converter can be used only when the CPU operating clock is w.
Rev. 3.00 May 15, 2007 Page 351 of 518 REJ09B0152-0300
Section 17 A/D Converter
Bit 3 2 1 0
Bit Name CH3 CH2 CH1 CH0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description Channel Select 3 to 0 Select the analog input channel. 00xx: No channel selected 0100: AN0 0101: AN1 0110: AN2 0111: AN3 1000: AN4 1001: AN5 101x: No channel selected 11xx: No channel selected The channel selection should be made while the ADSF bit is cleared to 0.
[Legend] x: Don't care.
17.3.3
A/D Start Register (ADSR)
ADSR starts and stops the A/D conversion.
Bit 7 Bit Name ADSF Initial Value 0 R/W R/W Description When this bit is set to 1, A/D conversion is started. When conversion is completed, the converted data is set in ADRR and at the same time this bit is cleared to 0. If this bit is written to 0, A/D conversion can be forcibly terminated. Ladder Resistance Select 0: Ladder resistance operates while the A/D converter is idle. 1: Ladder resistance is halted while the A/D converter is idle. The ladder resistance is always halted in standby mode, watch mode, or module standby mode, and at a reset. 5 to 0 All 1 Reserved These bits are always read as 1 and cannot be modified.
6
LADS
0
R/W
Rev. 3.00 May 15, 2007 Page 352 of 516 REJ09B0152-0300
Section 17 A/D Converter
17.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. When changing the conversion time or analog input channel, in order to prevent incorrect operation, first clear the bit ADSF to 0 in ADSR. 17.4.1 A/D Conversion
1. A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1, according to software. 2. When A/D conversion is completed, the result is transferred to the A/D result register. 3. On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2 is set to 1 at this time, an A/D conversion end interrupt request is generated. 4. The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADSF bit is automatically cleared to 0 and the A/D converter enters the wait state. 17.4.2 External Trigger Input Timing
The A/D converter can also start A/D conversion by input of an external trigger signal. External trigger input is enabled at the ADTRG pin when the ADTSTCHG bit in PMRB is set to 1* and the TRGE bit in AMR is set to 1. Then when the input signal edge designated in the ADTRGNEG bit in IEGR is detected at the ADTRG pin, the ADSF bit in ADSR will be set to 1, starting A/D conversion. Figure 17.2 shows the timing. Note: * The ADTRG input pin is shared with the TEST pin. Therefore when the pin is used as the ADTRG pin, reset should be cleared while the 0-fixed signal is input to the TEST pin. Then the ADTSTCHG bit should be set to 1 after the TEST signal is fixed.
ADTRG (when ADTRGNEG = 0) ADSF A/D conversion
Figure 17.2 External Trigger Input Timing
Rev. 3.00 May 15, 2007 Page 353 of 518 REJ09B0152-0300
Section 17 A/D Converter
17.4.3
Operating States of A/D Converter
Table 17.2 shows the operating states of the A/D converter. Table 17.2 Operating States of A/D Converter
Operating Mode
AMR
Reset
Reset
Active
Functions
Sleep
Retained
Watch
Retained
Subactive
Functions/ Retained*2
Sub-sleep Standby
Retained Retained
Module Standby
Retained
ADSR
Reset
Functions
Functions
Retained
Functions/ Retained*2
Functions/ Retained*2 Functions/ Retained*2
Retained
Retained
ADRR
Retained*1
Functions
Functions
Retained
Functions/ Retained*2
Retained
Retained
Notes: 1. Undefined at a power-on reset. 2. Function if w/2 is selected as the internal clock. Halted and retained otherwise.
17.5
Example of Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 17.3 shows the operation timing. 1. Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is stored in ADRR. At the same time bit ADSF is cleared to 0, and the A/D converter goes to the idle state. Bit IENAD = 1, so an A/D conversion end interrupt is requested. The A/D interrupt handling routine starts. The A/D conversion result is read and processed. The A/D interrupt handling routine ends.
2.
3. 4. 5. 6.
If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Rev. 3.00 May 15, 2007 Page 354 of 516 REJ09B0152-0300
Interrupt (IRRAD) Set*
IENAD A/D conversion starts Set* Set*
ADSF
Channel 1 (AN1) operating state Idle A/D conversion (1) Idle
A/D conversion (2)
Idle Read conversion result A/D conversion result (2)
ADRR
Read conversion result A/D conversion result (1)
Figures 17.4 and 17.5 show flowcharts of procedures for using the A/D converter.
Figure 17.3 Example of A/D Conversion Operation
Note: * indicates instruction execution by software.
Section 17 A/D Converter
Rev. 3.00 May 15, 2007 Page 355 of 518
REJ09B0152-0300
Section 17 A/D Converter
Start
Set A/D conversion speed and input channel Disable A/D conversion end interrupt
Start A/D conversion Read ADSR
No
ADSF = 0? Yes Read ADRR data
Yes
Perform A/D conversion? No End
Figure 17.4 Flowchart of Procedure for Using A/D Converter (Polling by Software)
Start
Set A/D conversion speed and input channel Enable A/D conversion end interrupt Start A/D conversion Yes Clear IRRAD bit in IRR2 to 0 Read ADRR data Yes
A/D conversion end interrupt generated? No
Perform A/D conversion? No End
Figure 17.5 Flowchart of Procedure for Using A/D Converter (Interrupts Used)
Rev. 3.00 May 15, 2007 Page 356 of 516 REJ09B0152-0300
Section 17 A/D Converter
17.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.6). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 17.7). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 17.7). * Nonlinearity error The error with respect to the ideal A/D conversion characteristics between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error. * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
Rev. 3.00 May 15, 2007 Page 357 of 518 REJ09B0152-0300
Section 17 A/D Converter
Digital output
111 110 101 100 011 010 001 000 1 8
Ideal A/D conversion characteristic
Quantization error
2 8
3 8
4 8
5 8
6 8
7 FS 8 Analog input voltage
Figure 17.6 A/D Conversion Accuracy Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage
Offset error
Figure 17.7 A/D Conversion Accuracy Definitions (2)
Rev. 3.00 May 15, 2007 Page 358 of 516 REJ09B0152-0300
Section 17 A/D Converter
17.7
17.7.1
Usage Notes
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 17.8). When converting a high-speed analog signal, a lowimpedance buffer should be inserted. 17.7.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND. Care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board.
This LSI Sensor output impedance to 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF
A/D converter equivalent circuit 10 k 48 pF
Figure 17.8 Example of Analog Input Circuit
Rev. 3.00 May 15, 2007 Page 359 of 518 REJ09B0152-0300
Section 17 A/D Converter
17.7.3 1. 2. 3.
Usage Notes
ADRR should be read only when the ADSF bit in ADSR is cleared to 0. Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. When A/D conversion is started after clearing module standby mode, wait for 10 clock cycles before starting A/D conversion.
Rev. 3.00 May 15, 2007 Page 360 of 516 REJ09B0152-0300
Section 18 Comparators
Section 18 Comparators
This LSI includes comparators to compare the input voltage and reference voltage. The block diagram of the comparators is shown in figure 18.1.
18.1
Features
* Reference voltage can be specified as internal power supply or external input (VCref). * When the internal power supply is selected as the reference voltage, programmable selection of sixteen types of voltages is possible. * When the internal power supply is selected, the hysteresis characteristics of the comparison result can be selected. * Two analog input channels Each channel includes its own comparator. * Use of module standby mode enables this module to be placed in standby mode independently when not used. (A comparator is halted as the initial value. For details, refer to section 5.4, Module Standby Function.)
Comparator + Comparator + CMDR
COMP0
CMCR0 CMCR1 26/30 25/30 24/30 10/30 9/30 R 9R [Legend] CMDR: Compare data register CMCR0: Compare control register 0 CMCR1: Compare control register 1 4R R R Interrupt generator Interrupt request
Figure 18.1 Block Diagram of Comparators
Rev. 3.00 May 15, 2007 Page 361 of 516 REJ09B0152-0300
ADCMS3AA_000020020900
Internal data bus
Selector
COMP1 VCref
Selector
Section 18 Comparators
18.2
Input/Output Pins
Table 18.1 shows the pin configuration of the comparators. Table 18.1 Pin Configuration
Pin Name Comparator reference voltage Analog input channel 0 Analog input channel 1 Abbreviation VCref COMP0 COMP1 I/O Input Input Input Function Comparator reference voltage pin (external input) Comparator analog input pin 0 Comparator analog input pin 1
18.3
Register Descriptions
The comparators have the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. * Compare control registers 0, 1 (CMCR0, CMCR1) * Compare data register (CMDR) 18.3.1 Compare Control Registers 0, 1 (CMCR0, CMCR1)
CMCR0 and CMCR1 control the comparators.
Bit 7 Bit Name CME Initial Value 0 R/W R/W Description Comparator Enable 0: Comparator halted 1: Comparator operates 6 CMIE 0 R/W Comparator Interrupt Enable 0: Disables a comparator interrupt 1: Enables a comparator interrupt 5 CMR 0 R/W Comparator Reference Voltage Select 0: Selects internal power supply as reference voltage 1: Reference voltage is input from VCref pin For the combination of the CMR and CMLS bits.
Rev. 3.00 May 15, 2007 Page 362 of 516 REJ09B0152-0300
Section 18 Comparators
Bit 4
Bit Name CMLS
Initial Value 0
R/W R/W
Description Comparator Hysteresis Select 0: Selects non-hysteresis 1: Selects hysteresis When CMR = 1, clear this bit to 0. For the combination of the CMR and CMLS bits.
3 2 1 0
CRS3 CRS2 CRS1 CRS0
0 0 0 0
R/W R/W R/W R/W
Internal Reference Voltage Select When CMR = 0 and CMLS = 0, the electric potential of VIL is selected as the internal power supply. When CMR = 0 and CMLS = 1, VIL will be as follows. When CMR = 1, CRS3 to CRS0 settings are disabled. VIH 0000: 11/30Vcc 0001: 12/30Vcc 0010: 13/30Vcc 0011: 14/30Vcc 0100: 15/30Vcc 0101: 16/30Vcc 0110: 17/30Vcc 0111: 18/30Vcc 1000: 19/30Vcc 1001: 20/30Vcc 1010: 21/30Vcc 1011: 22/30Vcc 1100: 23/30Vcc 1101: 24/30Vcc 1110: 25/30Vcc 1111: 26/30Vcc VIL 9/30Vcc 10/30Vcc 11/30Vcc 12/30Vcc 13/30Vcc 14/30Vcc 15/30Vcc 16/30Vcc 17/30Vcc 18/30Vcc 19/30Vcc 20/30Vcc 21/30Vcc 22/30Vcc 23/30Vcc 24/30Vcc
For the selectable range by the CRS bits, see section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 363 of 518 REJ09B0152-0300
Section 18 Comparators
Table 18.2 Combination of CMR and CMLS Bits
CMR 0 CMLS 0 Function Compares the internal power supply (voltage set for VIH by the CRS3 to CRS0 bits) and electric potential of the COMP pin. No hysteresis. 1 Compares the internal power supply and electric potential of the COMP pin. With hysteresis. VIH and VIL are set by the CRS3 to CRS0 bits. 1 0 1 Compares the electric potential of the VCref and COMP pins. No hysteresis. Setting prohibited
18.3.2
Compare Data Register (CMDR)
CMDR stores the result of comparing the analog input pin and reference voltage.
Bit 7, 6 5 Bit Name CMF1 Initial Value All 0 0 R/W
1
Description Reserved These bits are always read as 0.
R/(W)* COMP1 Interrupt Flag [Setting condition] When COMP1 interrupt occurs [Clearing condition] 0 is written to CMF1 after reading CMF1 = 1
4
CMF0
0
R/(W)*1 COMP0 Interrupt Flag [Setting condition] When COMP0 interrupt occurs [Clearing condition] 0 is written to CMF0 after reading CMF0 = 1
3, 2
All 0
Reserved These bits are always read as 0.
Rev. 3.00 May 15, 2007 Page 364 of 516 REJ09B0152-0300
Section 18 Comparators
Bit 1
Bit Name CDR1
Initial Value *
2
R/W R
Description [Setting condition] COMP1 pin > Reference voltage [Clearing condition] COMP1 pin Reference voltage
0
CDR0
*
2
R
[Setting condition] COMP0 pin > Reference voltage [Clearing condition] COMP0 pin Reference voltage
Notes: 1. Only 0 can be written to clear the flag. 2. Depends on the pin state and reference voltage.
18.4
18.4.1
Operation
Operation Sequence
The operation sequence of a comparator is as follows: 1. When using VCref, the pins to be used are enabled by the corresponding port mode registers. For details, see section 8, I/O Ports. 2. Select the reference voltage (CMR setting: internal power supply or VCref). When the internal power supply is selected as the reference voltage, select the hysteresis characteristics (CMLS setting) and reference voltage (CRS3 to CRS0 setting). 3. Set the comparator enable bit (CME). 4. After setting CME, wait for the conversion time (see section 21, Electrical Characteristics) so that the comparator becomes stabilized. 5. Read from CDR. 6. After reading the CMF flag, write 0 to it (reading the CMF flag can be performed simultaneously with step 5). 7. If an interrupt is to be generated, set the comparator interrupt enable bit (CMIE). Note: Steps 2 and 3 can be done simultaneously by writing to the entire register.
Rev. 3.00 May 15, 2007 Page 365 of 518 REJ09B0152-0300
Section 18 Comparators
18.4.2
Hysteresis Characteristics of Comparator
Figure 18.2 shows CDR when hysteresis is or is not selected by the CMLS bit CMCR and the input voltage to the COMP pins. The hysteresis characteristics for the comparison result (CDR) by the comparator can be selected by the CMLS bit, as shown in figure 18.2.
When CMR = 0 and CRS3 to CRS0 = B'1000 (VIH = 19/30Vcc, VIL = 17/30Vcc) COMP pin input voltage
19/30 Vcc 17/30 Vcc
CDR (CMLS = 0) CDR (CMLS = 1)
Figure 18.2 Hysteresis/Non-Hysteresis Selection by CDR 18.4.3 Interrupt Setting
When the CDR bit is read while the comparator interrupt is enabled and both the CME and CMIE bits are set to 1, it is latched in the internal latch. When a difference occurs between the output of the latch and the CDR bit, the interrupt is generated. While the CDR bit is being read, the interrupt is masked.
Rev. 3.00 May 15, 2007 Page 366 of 516 REJ09B0152-0300
Section 18 Comparators
To set the interrupt, follow the procedure shown in figure 18.3 or 18.4.
[1] [2] [3] [4] Set the CME bit. Wait a conversion time for the comparator stabilized. Read the CDR bit. Set the CMIE bit. Read the CDR bit. At this time, the CDR bit is latched in the internal latch for the comparator and the internal interrupt enable signal is asserted. As the relationship between the voltage on the COMP pin and reference voltage is changed, a difference occurs between the output level of the internal latch and the CDR bit. Then an interrupt is generated. Clear the CMF bit in the interrupt handler. When reading the CMF bit for clearing it, the CDR bit is also read since those bits are in the same register. Therefore, the output of the internal latch is updated. Go to step [5] to continue use of the interrupt. Clear the CMIE bit to clear the interrupt setting and clear the CME bit to stop the comparator. Clearing the CMIE bit negates the internal interrupt enable signal. The interrupt flag may be set depending on the internal states of the comparator, pin states, the timing of setting the internal interrupt enable signal shown in step [4], and the timing of the CDR bit latched. To avoid this, execute steps [2] to [4] continuously or ensure that the CMF bit is cleared using the I bit in CCR as shown in figure 18.4.
[5]
[6]
[7]
When CMR = 0 and CMRS3 to CMRS0 = B'1000 (VIH = 19/30 Vcc)
19/30 Vcc Voltage on COMP pin
Conversion time CDR (CMLS = 0) CME [1] CMIE [3] Interrupt enable signal Stabilization time (conversion time) CDR read signal Internal latch for comparator CMF [5] [6] [5] [2] Unstable [4] [4] [6] [6]
Conversion time
[7] [7]
[6] [6] [6]
Figure 18.3 Procedure for Setting Interrupt (1)
Rev. 3.00 May 15, 2007 Page 367 of 518 REJ09B0152-0300
Section 18 Comparators
Set I bit in CCR to 1 Set CME bit to 1 Set CMIE bit to 1 Read CDR bit Clear CMF bit Clear I bit in CCR to 0
Disable interrupts by the I bit. Set the comparator enable bit to 1. Wait for the comparator stabilized. Enable the interrupt. Actually, the interrupt is masked by the I bit. The CDR bit is latched in the internal latch by reading it. Clear the interrupt request flag. Enable interrupts by the I bit.
Figure 18.4 Procedure for Setting Interrupt (2)
18.5
Usage Notes
1. The COMP pin whose channel is operating as a comparator becomes a comparator analog input pin. It cannot be used for any other function. 2. When external input is used as the reference voltage (CMR0 = 1 or CMR1 = 1), the VCref pin cannot be used for any other function. 3. To stop the operation of a comparator, clear the CME0 and CME1 bits in CMCR0 and CMCR1 to 0, before clearing the COMPCKSTP bit in CKSTPR2 to 0. 4. If the LSI enters the standby mode or watch mode when a comparator is operating, the internal operation of the comparator is maintained. Since the comparator operates even in standby mode or watch mode, it returns to the same mode after the specified interrupt is canceled, though the current for the comparator is consumed. If a comparator is not required to return to the standby mode or watch mode when an interrupt is canceled and the current consumption needs to be reduced, stop the comparator by clearing the CME0 and CME1 bits in CMCR0 and CMCR1 to 0 before shifting the mode.
Rev. 3.00 May 15, 2007 Page 368 of 516 REJ09B0152-0300
Section 19 Power-On Reset Circuit
Section 19 Power-On Reset Circuit
This LSI has an on-chip power-on reset circuit. A block diagram of the power-on reset circuit is shown in figure 19.1.
19.1
Feature
* Power-on reset circuit An internal reset signal is generated at turning the power on by externally connecting a capacitor.
Vcc
Vcc Rp RES
CK R
3-bit counter
COUT
R Voltage detector Q S
Internal reset signal
CRES
Figure 19.1 Power-On Reset Circuit
Rev. 3.00 May 15, 2007 Page 369 of 516 REJ09B0152-0300
Section 19 Power-On Reset Circuit
19.2
19.2.1
Operation
Power-On Reset Circuit
The operation timing of the power-on reset circuit is shown in figure 19.2. As the power supply voltage rises, the capacitor, which is externally connected to the RES pin, is gradually charged through the on-chip pull-up resistor (Rp). The low level of the RES pin is sent to the LSI and the whole LSI is reset. When the level of the RES pin reaches to the predetermined level, a voltage detection circuit detects it. Then a 3-bit counter starts counting up. When the 3-bit counter counts for 8 times, an overflow signal is generated and an internal reset signal is negated. The capacitance (CRES) which is connected to the RES pin can be computed using the following formula; where the RES rising time is t. For the on-chip resistor (Rp), see section 21, Electrical Characteristics. The power supply rising time (t_vtr) should be shorter than half the RES rising time (t). The RES rising time (t) is also should be longer than the oscillation stabilization time (trc).
CRES = t Rp (t > trc, t > t_vtr x 2)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a power-on reset may not occur.
t_vtr Vcc
t_vtr x 2 RES V_rst
Internal reset signal
t_cr
t_out (eight states)
Figure 19.2 Power-On Reset Circuit Operation Timing
Rev. 3.00 May 15, 2007 Page 370 of 516 REJ09B0152-0300
Section 20 List of Registers
Section 20 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * * 2. * * * Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The data bus width is indicated. The number of access states is indicated.
Register bits Bit configurations of the registers are described in the same order as the register addresses. Reserved bits are indicated by in the bit name column. When the bit number is in the bit name column, it indicates that the entire register is allocated to a counter or data. * When registers consist of 16 bits, bits are described from the MSB side. 3. Register states in each operating mode * Register states are described in the same order as the register addresses. * The register states described here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Rev. 3.00 May 15, 2007 Page 371 of 516 REJ09B0152-0300
Section 20 List of Registers
20.1
Register Addresses (Address Order)
The data bus width indicates the number of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Register Name Flash memory control register 1 Flash memory control register 2 Flash memory power control register Erase block register 1 Flash memory enable register RTC interrupt flag register Second data register/free running counter data register Minute data register Hour data register Day-of-week data register RTC control register 1 RTC control register 2 Clock source select register I C bus control register 1 I C bus control register 2 I C bus mode register I C bus interrupt enable register I2C bus status register Slave address register I C bus transmit data register I C bus receive data register
2 2 2 2 2 2
Abbreviation FLMCR1 FLMCR2 FLPWCR EBR1 FENR RTCFLG RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 RTCCSR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR
Address H'F020 H'F021 H'F022 H'F023 H'F02B H'F067 H'F068 H'F069 H'F06A H'F06B H'F06C H'F06D H'F06F H'F078 H'F079 H'F07A H'F07B H'F07C H'F07D H'F07E H'F07F
Module Name ROM ROM ROM ROM ROM RTC RTC RTC RTC RTC RTC RTC RTC IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 IIC2 IIC2
Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 3.00 May 15, 2007 Page 372 of 516 REJ09B0152-0300
Section 20 List of Registers
Register Name Port function control register Port pull-up control register 8 Port pull-up control register 9 Port open-drain control register 9 Timer mode register B1 Timer counter B1/ Timer load register B1 Compare control register 0 Compare control register 1 Compare data register SS control register H SS control register L SS mode register SS enable register SS status register SS receive data register SS transmit data register Timer mode register W Timer control register W Timer interrupt enable register W Timer status register W Timer I/O control register 0 Timer I/O control register 1 Timer counter General register A General register B General register C General register D
Abbreviation PFCR PUCR8 PUCR9 PODR9 TMB1 TCB1 (R)/ TLB1 (W) CMCR0 CMCR1 CMDR SSCRH SSCRL SSMR SSER SSSR SSRDR SSTDR TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT GRA GRB GRC GRD
Address H'F085 H'F086 H'F087 H'F08C H'F0D0 H'F0D1 H'F0DC H'F0DD H'F0DE H'F0E0 H'F0E1 H'F0E2 H'F0E3 H'F0E4 H'F0E9 H'F0EB H'F0F0 H'F0F1 H'F0F2 H'F0F3 H'F0F4 H'F0F5 H'F0F6 H'F0F8 H'F0FA H'F0FC H'F0FE
Module Name System I/O ports I/O ports I/O ports Timer B1 Timer B1
Data Bus Access Width State 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2
Comparator 8 Comparator 8 Comparator 8 SSU* SSU* SSU* SSU* SSU* SSU*
1
8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16
1
1
1
1
1
SSU*1 Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W Timer W
Rev. 3.00 May 15, 2007 Page 373 of 516 REJ09B0152-0300
Section 20 List of Registers
Register Name
Abbreviation
Address H'FF8C H'FF8E H'FF91 H'FF92 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D H'FFA6 H'FFA7 H'FFB0
Module Name AEC*2 AEC*2 SCI3 AEC* AEC* AEC* AEC* AEC* SCI3 SCI3 SCI3 SCI3 SCI3 SCI3 SCI3 IrDA WDT*
3 2 2
Data Bus Access Width State 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2
Event counter PWM compare register ECPWCR Event counter PWM data register Serial port control register Input pin edge select register Event counter control register Event counter control/status register Event counter H Event counter L Serial mode register 3 Bit rate register 3 Serial control register 3 Transmit data register 3 Serial status register 3 Receive data register 3 Serial extended mode register IrDA control register Timer mode register WD Timer control/status register WD1 Timer control/status register WD2 Timer counter WD A/D result register A/D mode register A/D start register
ECPWDR
SPCR AEGSR ECCR ECCSR ECH ECL SMR3 BRR3 SCR3 TDR3 SSR3 RDR3 SEMR IrCR TMWD
2
2
2
TCSRWD1 H'FFB1 TCSRWD2 H'FFB2 TCWD ADRR AMR ADSR H'FFB3 H'FFBC H'FFBE H'FFBF
WDT*3 WDT* WDT*
3 3
A/D converter A/D converter A/D converter
Rev. 3.00 May 15, 2007 Page 374 of 516 REJ09B0152-0300
Section 20 List of Registers
Register Name Port mode register 1 Port mode register 3 Port mode register B Port data register 1 Port data register 3 Port data register 8 Port data register 9 Port data register B Port pull-up control register 1 Port pull-up control register 3 Port control register 1 Port control register 3 Port control register 8 Port control register 9 System control register 1 System control register 2 Interrupt edge select register Interrupt enable register 1 Interrupt enable register 2 Oscillator control register Interrupt flag register 1 Interrupt flag register 2 Clock stop register 1 Clock stop register 2
Abbreviation PMR1 PMR3 PMRB PDR1 PDR3 PDR8 PDR9 PDRB PUCR1 PUCR3 PCR1 PCR3 PCR8 PCR9 SYSCR1 SYSCR2 IEGR IENR1 IENR2 OSCCR IRR1 IRR2
Address H'FFC0 H'FFC2 H'FFCA H'FFD4 H'FFD6 H'FFDB H'FFDC H'FFDE H'FFE0 H'FFE1 H'FFE4 H'FFE6 H'FFEB H'FFEC H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7
Module Name I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports I/O ports System System Interrupts Interrupts Interrupts System Interrupts Interrupts System System
Data Bus Access Width State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CKSTPR1 H'FFFA CKSTPR2 H'FFFB
Notes: 1. SSU: Synchronous serial communication unit 2. AEC: Asynchronous event counter 3. WDT: Watchdog timer
Rev. 3.00 May 15, 2007 Page 375 of 516 REJ09B0152-0300
Section 20 List of Registers
20.2
Register Bits
Register bit names of the on-chip peripheral modules are described below. The 16-bit register is indicated in two rows, 8 bits for each row.
Register Abbreviation FLMCR1 FLMCR2 FLPWCR EBR1 FENR RTCFLG RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 RTCCSR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR PFCR PUCR8 PUCR9 PODR9 TMB1 TCB1 (R)/ TLB1 (W) Bit 7 FLER PDWND FLSHE FOIFG BSY BSY BSY BSY RUN FOIE ICE BBSY MLS TIE TDRE SVA6 ICDRT7 ICDRR7 TMB17 Bit 7 Bit 6 SWE WKIFG SC12 MN12 12/24 WKIE RCS6 RCVD SCP WAIT TEIE TEND SVA5 ICDRT6 ICDRR6 TMB16 Bit 6 Bit 5 ESU DYIFG SC11 MN11 HR11 PM DYIE RCS5 MST SDAO RIE RDRF SVA4 ICDRT5 ICDRR5 Bit 5 Bit 4 PSU EB4 HRIFG SC10 MN10 HR10 RST HRIE SUB32K TRS SDAOP NAKIE NACKF SVA3 ICDRT4 ICDRR4 SSUS PUCR84 Bit 4 Bit 3 EV EB3 MNIFG SC03 MN03 HR03 INT MNIE RCS3 CKS3 SCLO BCWP STIE STOP SVA2 ICDRT3 ICDRR3 IRQ1S1 PUCR83 PUCR93 P93ODR Bit 3 Bit 2 PV EB2 1SEIFG SC02 MN02 HR02 WK2 1SEIE RCS2 CKS2 BC2 ACKE AL/OVE SVA1 ICDRT2 ICDRR2 IRQ1S0 PUCR82 PUCR92 P92ODR TMB12 Bit 2 Bit 1 E EB1 05SEIFG SC01 MN01 HR01 WK1 05SEIE RCS1 CKS1 IICRST BC1 ACKBR AAS SVA0 ICDRT1 ICDRR1 IRQ0S1 PUCR91 P91ODR TMB11 Bit 1 Bit 0 P EB0 025SEIFG SC00 MN00 HR00 WK0 025SEIE RCS0 CKS0 BC0 ACKBT ADZ FS ICDRT0 ICDRR0 IRQ0S0 PUCR90 P90ODR TMB10 Bit 0 Timer B1 System I/O ports IIC2 RTC Module Name ROM
Rev. 3.00 May 15, 2007 Page 376 of 516 REJ09B0152-0300
Section 20 List of Registers
Register Abbreviation CMCR0 CMCR1 CMDR SSCRH SSCRL SSMR SSER SSSR SSRDR SSTDR TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT Bit 7 CME0 CME1 MSS MLS TE -- Bit 7 Bit 7 CTS CCLR OVIE OVF -- -- TCNT15 TCNT7 GRA GRA15 GRA7 GRB GRB15 GRB7 GRC GRC15 GRC7 GRD GRD15 GRD7 ECPWCR Bit 6 CMIE0 CMIE1 BIDE SSUMS CPOS RE ORER Bit 6 Bit 6 -- CKS2 -- -- IOB2 IOD2 TCNT14 TCNT6 GRA14 GRA6 GRB14 GRB6 GRC14 GRC6 GRD14 GRD6 Bit 5 CMR0 CMR1 CMF1 SOOS SRES CPHS RSSTP -- Bit 5 Bit 5 BUFEB CKS1 -- -- IOB1 IOD1 TCNT13 TCNT5 GRA13 GRA5 GRB13 GRB5 GRC13 GRC5 GRD13 GRD5 Bit 4 CMLS0 CMLS1 CMF0 SOL SCKOS -- -- -- Bit 4 Bit 4 BUFEA CKS0 -- -- IOB0 IOD0 TCNT12 TCNT4 GRA12 GRA4 GRB12 GRB4 GRC12 GRC4 GRD12 GRD4 Bit 3 CRS03 CRS13 SOLP CSOS -- TEIE TEND Bit 3 Bit 3 -- TOD IMIED IMFD -- -- TCNT11 TCNT3 GRA11 GRA3 GRB11 GRB3 GRC11 GRC3 GRD11 GRD3 Bit 2 CRS02 CRS12 SCKS -- CKS2 TIE TDRE Bit 2 Bit 2 PWMD TOC IMIEC IMFC IOA2 IOC2 TCNT10 TCNT2 GRA10 GRA2 GRB10 GRB2 GRC10 GRC2 GRD10 GRD2 Bit 1 CRS01 CRS11 CDR1 CSS1 -- CKS1 RIE RDRF Bit 1 Bit 1 PWMC TOB IMIEB IMFB IOA1 IOC1 TCNT9 TCNT1 GRA9 GRA1 GRB9 GRB1 GRC9 GRC1 GRD9 GRD1 Bit 0 CRS00 CRS10 CDR0 CSS0 -- CKS0 CEIE CE Bit 0 Bit 0 PWMB TOA IMIEA IMFA IOA0 IOC0 TCNT8 TCNT0 GRA8 GRA0 GRB8 GRB0 GRC8 GRC0 GRD8 GRD0 ECPWCR8 ECPWCR0 ECPWDR8 ECPWDR0
Module Name Comparator
SSU*1
Timer W
ECPWCR15 ECPWCR14 ECPWCR13 ECPWCR12 ECPWCR11 ECPWCR10 ECPWCR9 ECPWCR7 ECPWCR6 ECPWCR5 ECPWCR4 ECPWCR3 ECPWCR2 ECPWCR1
AEC*2
ECPWDR
ECPWDR15 ECPWDR14 ECPWDR13 ECPWDR12 ECPWDR11 ECPWDR10 ECPWDR9 ECPWDR7 ECPWDR6 ECPWDR5 ECPWDR4 ECPWDR3 ECPWDR2 ECPWDR1
Rev. 3.00 May 15, 2007 Page 377 of 516 REJ09B0152-0300
Section 20 List of Registers
Register Abbreviation SPCR AEGSR ECCR ECCSR ECH ECL SMR3 BRR3 SCR3 TDR3 SSR3 RDR3 SEMR IrCR TMWD TCSRWD1 TCSRWD2 TCWD ADRR Bit 7 AHEGS1 ACKH1 OVH ECH7 ECL7 COM BRR7 TIE TDR7 TDRE RDR7 IrE B6WI OVF TCW7 ADR9 ADR1 AMR ADSR PMR1 PMR3 PMRB PDR1 PDR3 PDR8 PDR9 PDRB PUCR1 ADSF Bit 6 AHEGS0 ACKH0 OVL ECH6 ECL6 CHR BRR6 RIE TDR6 RDRF RDR6 IrCKS2 TCWE B5WI TCW6 ADR8 ADR0 TRGE LADS Bit 5 ALEGS1 ACKL1 ECH5 ECL5 PE BRR5 TE TDR5 OER RDR5 IrCKS1 B4WI WT/IT TCW5 ADR7 CKS1 IRQAEC PB5 Bit 4 SPC3 ALEGS0 ACKL0 CH2 ECH4 ECL4 PM BRR4 RE TDR4 FER RDR4 IrCKS0 TCSRWE B3WI TCW4 ADR6 CKS0 FTCI P84 PB4 Bit 3 AIEGS1 PWCK2 CUEH ECH3 ECL3 STOP BRR3 MPIE TDR3 PER RDR3 ABCS CKS3 B2WI IEOVF TCW3 ADR5 CH3 AEVL ADTSTCHG P83 P93 PB3 Bit 2 AIEGS0 PWCK1 CUEL ECH2 ECL2 MP BRR2 TEIE TDR2 TEND RDR2 CKS2 WDON TCW2 ADR4 CH2 CLKOUT P12 P32 P82 P92 PB2 PUCR12 Bit 1 SCINV1 ECPWME PWCK0 CRCH ECH1 ECL1 CKS1 BRR1 CKE1 TDR1 MPBR RDR1 CKS1 B0WI TCW1 ADR3 CH1 TMOW IRQ1 P11 P31 P91 PB1 PUCR11 Bit 0 SCINV0 CRCL ECH0 ECL0 CKS0 BRR0 CKE0 TDR0 MPBT RDR0 CKS0 WRST TCW0 ADR2 CH0 AEVH VCref IRQ0 P10 P30 P90 PB0 PUCR10
Module Name SCI3 AEC*2
SCI3
IrDA WDT*3
A/D converter
I/O ports
Rev. 3.00 May 15, 2007 Page 378 of 516 REJ09B0152-0300
Section 20 List of Registers
Register Abbreviation PUCR3 PCR1 PCR3 PCR8 PCR9 SYSCR1 SYSCR2 IEGR IENR1 IENR2 OSCCR IRR1 IRR2 CKSTPR1 CKSTPR2 Bit 7 SSBY NMIEG IENRTC SUBSTP Bit 6 STS2 IENAD RFCUT IRRAD S3CKSTP TWCKSTP Bit 5 STS1 ADTRGNEG SUBSEL IICCKSTP Bit 4 PCR84 STS0 NESEL ADCKSTP SSUCKSTP Bit 3 PCR83 PCR93 LSON DTON AECCKSTP Bit 2 PUCR32 PCR12 PCR32 PCR82 PCR92 TMA3 MSON IENEC2 IENTB1 IRREC2 IRRTB1 TB1CKSTP WDCKSTP Bit 1 PUCR31 PCR11 PCR31 PCR91 MA1 SA1 IEG1 IEN1 OSCF IRRI1 FROMCKSTP COMPCKSTP Bit 0 PUCR30 PCR10 PCR30 PCR90 MA0 SA0 IEG0 IEN0 IENEC IRRI0 IRREC
Module Name I/O ports
System
Interrupts
System Interrupts
RTCCKSTP System
Notes: 1. SSU: Synchronous serial communication unit 2. AEC: Asynchronous event counter 3. WDT: Watchdog timer
Rev. 3.00 May 15, 2007 Page 379 of 516 REJ09B0152-0300
Section 20 List of Registers
20.3
Register States in Each Operating Mode
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Active Sleep Watch Subactive Subsleep Standby Initialized Initialized Timer B1 System I/O ports IIC2 RTC Module ROM
Register Abbreviation FLMCR1 FLMCR2 FLPWCR EBR1 FENR RTCFLG RSECDR RMINDR RHRDR RWKDR RTCCR1 RTCCR2 RTCCSR ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR PFCR PUCR8 PUCR9 PODR9 TMB1 TCB1/TLB1
Rev. 3.00 May 15, 2007 Page 380 of 516 REJ09B0152-0300
Section 20 List of Registers Register Abbreviation CMCR0 CMCR1 CMDR SSCRH SSCRL SSMR SSER SSSR SSRDR SSTDR TMRW TCRW TIERW TSRW TIOR0 TIOR1 TCNT GRA GRB GRC GRD ECPWCR ECPWDR SPCR AEGSR ECCR ECCSR ECH ECL
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep Watch
Subactive Subsleep Standby
Module Comparator
SSU*
1
Timer W
AEC*
2
SCI3 AEC*
2
Rev. 3.00 May 15, 2007 Page 381 of 516 REJ09B0152-0300
Section 20 List of Registers Register Abbreviation SMR3 BRR3 SCR3 TDR3 SSR3 RDR3 SEMR IrCR TMWD TCSRWD1 TCSRWD2 TCWD ADRR AMR ADSR PMR1 PMR3 PMRB PDR1 PDR3 PDR8 PDR9 PDRB PUCR1 PUCR3 PCR1 PCR3 PCR8 PCR9
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep Watch Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Subactive Subsleep Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module SCI3
IrDA WDT*
3
A/D converter
I/O ports
Rev. 3.00 May 15, 2007 Page 382 of 516 REJ09B0152-0300
Section 20 List of Registers Register Abbreviation SYSCR1 SYSCR2 IEGR IENR1 IENR2 OSCCR IRR1 IRR2 CKSTPR1 CKSTPR2
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Active
Sleep Watch
Subactive Subsleep Standby
Module System
Interrupts
System Interrupts
System
Notes: is not initialized. 1. SSU: Synchronous serial communication unit 2. AEC: Asynchronous event counter 3. WDT: Watchdog timer
Rev. 3.00 May 15, 2007 Page 383 of 516 REJ09B0152-0300
Section 20 List of Registers
Rev. 3.00 May 15, 2007 Page 384 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Section 21 Electrical Characteristics
21.1 Absolute Maximum Ratings for F-ZTAT Version
Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Input voltage Other than port B Port B Operating temperature Symbol VCC AVCC Vin AVin Topr Value -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -20 to +75 (general 2 specifications)* -40 to +85 (wide temperature range 2 specifications)* Storage temperature Tstg -55 to +125 C Notes: 1. Permanent damage may occur to the LSI if absolute maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. The operating temperature range for flash memory programming/erasing is Ta = 0 to +75C. Unit V V V V C Note *1
Rev. 3.00 May 15, 2007 Page 385 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.2
21.2.1
Electrical Characteristics for F-ZTAT Version
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
(1) System clock oscillator selected (10-MHz version)
fosc (MHz)
fW (kHz)
10.0
38.4 32.768
4.0 1.8 2.7 3.6 Vcc (V) 1.8 2.7 3.6 Vcc (V) * All operating modes * Refer to note Rosc/32 used (reference value)
* Active (high-speed) mode * Sleep (high-speed) mode 81.25
fW (kHz)
9.375
2.7 3.6 Vcc (V) 1.8 * All operating modes (2) System clock oscillator selected (4-MHz version)
fW (kHz)
38.4 32.768
fosc (MHz)
4.2 2.0 1.8 2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
2.7 3.6 Vcc (V) 1.8 * All operating modes * Refer to note Rosc/32 used (reference value)
fW (kHz)
81.25
9.375
2.7 3.6 Vcc (V) 1.8 * All operating modes Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation stabilization time has elapsed after switching on.
Figure 21.1 Power Supply Voltage and Oscillation Frequency Range (1)
Rev. 3.00 May 15, 2007 Page 386 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(3) On-chip oscillator selected Rosc used (reference value)
fW (kHz)
38.4 32.768
fosc (MHz)
2.6 0.3 1.8 2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 3.6 Vcc (V) * All operating modes * Refer to note Rosc/32 used (reference value)
fW (kHz)
81.25
9.375
1.8 2.7 3.6 Vcc (V) * All operating modes Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation stabilization time has elapsed after switching on.
Figure 21.2 Power Supply Voltage and Oscillation Frequency Range (2)
Rev. 3.00 May 15, 2007 Page 387 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version) 10.0 38.4 32.768 19.2
SUB (kHz) (MHz)
16.384 9.6 8.192 4.8 4.096
4.0
1.8
2.7 3.6 Vcc (V)
1.8
2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
1250
62.5
(kHz)
Rosc/32 used (reference value) 81.25
SUB (kHz)
1.172 1.8 2.7 3.6 Vcc (V)
1.8
2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
Figure 21.3 Power Supply Voltage and Operating Frequency Range (1)
Rev. 3.00 May 15, 2007 Page 388 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(2) System clock oscillator selected (4-MHz version) 38.4 32.768
SUB (kHz) (MHz)
4.2 2.0
19.2 16.384 9.6 8.192 4.8 4.096
1.8 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 3.6 Vcc (V) * Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
525
(kHz)
Rosc/32 used (reference value) 31.25 81.25
SUB (kHz)
1.8 2.7 3.6 Vcc (V)
1.172 1.8 2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
Figure 21.4 Power Supply Voltage and Operating Frequency Range (2)
Rev. 3.00 May 15, 2007 Page 389 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(3) On-chip oscillator selected 38.4 32.768 19.2
SUB (kHz)
16.384 9.6 8.192 4.8 4.096
Rosc used (reference value)
(MHz)
2.6 0.3 1.8 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 3.6 Vcc (V) * Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
Rosc used (reference value) 325
Rosc/32 used (reference value)
(kHz)
4.6875
SUB (kHz)
1.8 2.7 3.6 Vcc (V)
81.25
1.172 1.8 2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
Figure 21.5 Power Supply Voltage and Operating Frequency Range (3)
Rev. 3.00 May 15, 2007 Page 390 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version)
10.0
38.4
4.0
SUB (kHz)
(MHz)
32.768
1.8
2.7
3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 * All operating modes
Rosc/32 used (reference value)
3.6 AVcc (V)
81.25
SUB (kHz)
9.375
1.8 2.7 * All operating modes
(2) System clock oscillator selected (4-MHz version)
3.6 AVcc (V)
38.4
4.2
2.0
1.8 2.7 3.6 AVcc (V)
SUB (kHz)
(MHz)
32.768
* Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 * All operating modes
3.6 AVcc (V)
Rosc/32 used (reference value)
81.25
SUB (kHz)
9.375
1.8 2.7 * All operating modes
3.6 AVcc (V)
Figure 21.6 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (1)
Rev. 3.00 May 15, 2007 Page 391 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(3) On-chip oscillator selected Rosc used (reference value)
SUB (kHz)
38.4
32.768
(MHz)
2.6
0.3
1.8
2.7
3.6 AVcc (V)
1.8
2.7
3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* All operating modes
Rosc/32 used (reference value)
SUB (kHz)
81.25
9.375
1.8 2.7 * All operating modes
3.6 AVcc (V)
Figure 21.7 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (2)
Rev. 3.00 May 15, 2007 Page 392 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.2.2
DC Characteristics
Table 21.2 lists the DC characteristics. Table 21.2 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values Item Input high voltage Symbol VIH Applicable Pins Test Condition RES, TEST, 3 NMI* , AEVL, AEVH, ADTRG, SCK3, IRQAEC IRQ0* , IRQ1*
4 4
Min. 0.9VCC
Typ. --
Max. VCC + 0.3
Unit V
Notes
0.9VCC 0.8VCC 0.9VCC 0.9VCC 0.8VCC
-- -- -- -- --
AVCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3
RXD3, IrRXD OSC1 X1 P10 to P12, P30 to P32, P82 to P84, P90 to P93, SSI, SSO, SSCK, SCS, FTCI, FTIOA, FTIOB, FTIOC, FTIOD, E7_0 to E7_2, SCL, SDA PB0 to PB5
0.8VCC
--
AVCC + 0.3
Rev. 3.00 May 15, 2007 Page 393 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Values Item Input low voltage Symbol VIL Applicable Pins Test Condition RES, TEST, 3 NMI* , IRQ0, IRQ1, IRQAEC, AEVL, AEVH, ADTRG, SCK3 RXD3, IrRXD OSC1 X1 P10 to P12, P30 to P32, P82 to P84, P90 to P93, SCL, SDA, PB0 to PB5, SSI, SSO, SSCK, SCS, FTCI, FTIOA, FTIOB, FTIOC, FTIOD, E7_0 to E7_2, SCL, SDA Output high voltage VOH P10 to P12, P30 to P32, P90 to P93 P82 to P84 Min. -0.3 Typ. -- Max. 0.1VCC Unit V Notes
-0.3 -0.3 -0.3 -0.3
-- -- -- --
0.2VCC 0.1VCC 0.1VCC 0.2VCC
-IOH = 1.0 mA VCC - 1.0 -- Vcc = 2.7 V to 3.6 V -IOH = 0.1 mA VCC - 0.3 --
-- -- -- -- 0.5
V
-IOH = 1.0 mA VCC - 1.0 -- VCC = 2.7 V to 3.6 V -IOH = 0.1 mA VCC - 0.3 -- -- --
Output low VOL voltage
P10 to P12, P30 to P32, P90 to P93 P82 to P84
IOL = 0.4 mA
V
IOL = 15 mA, -- Vcc = 2.7 V to 3.6 V IOL = 10 mA, -- Vcc = 2.2 V to 3.6 V IOL = 8 mA -- --
-- -- -- --
1.0 0.5 0.5 0.4
SCL, SDA
IOL = 3.0 mA
Rev. 3.00 May 15, 2007 Page 394 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Values Item Symbol Applicable Pins Test Condition TEST, NMI* , OSC1, X1, P10 to P12, P30 to P32, P82 to P84, P90 to P93, E7_0 to E7_2
3
Min. --
Typ. --
Max. 1.0
Unit A
Notes
Input/output | IIL | leakage current
VIN = 0.5 V to VCC - 0.5 V
PB0 to PB5 Pull-up MOS -Ip current P10 to P12, P30 to P32, P82 to P84, P90 to P93 All input pins except power supply pin VCC
VIN = 0.5 V to AVCC - 0.5 V VCC = 3 V, VIN = 0 V
-- 30
-- --
1.0 180 A
Input CIN capacitance Active mode IOPE1 supply current
f = 1 MHz, VIN =0 V, Ta = 25C Active (highspeed) mode, VCC = 1.8 V, fOSC = 2 MHz Active (highspeed) mode, VCC = 3 V, fOSC = ROSC
--
--
15.0
pF
--
1.1
--
mA
Max. guideline = 1.1 x 12 typ.* * Max. guideline = 1.1 x 12 typ.* * Reference value ** 4-MHz version ** 10-MHz version
12 12
--
1.2
--
Active (highspeed) mode, VCC = 3 V, fOSC = 4.2 MHz Active (highspeed) mode, VCC = 3 V, fOSC = 10 MHz
--
2.6
4.0
--
6.0
10.0
Rev. 3.00 May 15, 2007 Page 395 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition VCC Active (mediumspeed) mode, VCC = 1.8 V, fOSC = 2 MHz, osc/64 Active (mediumspeed) mode, VCC = 3 V, fOSC = 4.2 MHz, osc/64 Active (mediumspeed) mode, VCC = 3 V, fOSC = 10 MHz, osc/64 Sleep mode supply current ISLEEP VCC VCC = 1.8 V, fOSC = 2 MHz Min. -- Typ. 0.4 Max. -- Unit Notes mA Max. guideline = 1.1 x 12 typ.* * ** 4-MHz version
12
Active mode IOPE2 supply current
--
0.7
1.1
--
0.8
1.3
** 10-MHz version
12
--
0.9
--
mA
Max. guideline = 1.1 x 12 typ.* * ** 4-MHz version ** 10-MHz version
12 12
VCC = 3 V, fOSC = 4.2 MHz VCC = 3 V, fOSC = 10 MHz ISUB Subactive mode supply current VCC VCC = 2.7 V, 32-kHz crystal resonator (SUB = W/8) VCC = 2.7 V, 32-kHz crystal resonator (SUB = W/2) VCC = 2.7 V, on-chip oscillator/32 (SUB = W = ROSC/32) VCC = 2.7 V, 32-kHz crystal resonator (SUB = W)
--
2.0
3.2
--
4.2
6.4
--
7.0
--
A
** Reference value ** Reference value ** Reference value **
12 12 12
12
--
25
--
--
80
--
--
45
75
Rev. 3.00 May 15, 2007 Page 396 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Values Item Symbol Applicable Pins Test Condition VCC VCC = 2.7 V, 32-kHz crystal resonator (SUB = W/2) VCC = 2.7 V, on-chip oscillator/32 (SUB = W = ROSC/32) VCC = 2.7 V, 32-kHz crystal resonator (SUB = W) Watch mode IWATCH supply current VCC VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator VCC = 2.7 V, 32-kHz crystal resonator Standby ISTBY mode supply current VCC VCC = 3.0 V, Ta = 25C, 32-kHz crystal resonator not used 32-kHz crystal resonator not used RAM data retaining voltage Permissible output low current (per pin) VRAM VCC Min. -- Typ. 3.5 Max. -- Unit Notes A ** Reference value ** Reference value **
12 12 12
ISUBSP Subsleep mode supply current
--
34
--
--
5.1
16.0
--
0.5
--
A
** Reference value **
12
12
--
1.5
5.0
--
0.1
--
A
** Reference value
12
--
1.0
5.0
**
12
1.5
--
--
V
IOL
Output pins except port 8 Port 8 Output pins except port 8 Port 8
-- -- -- --
-- -- -- --
0.5 15.0 20.0 45.0
mA
Permissible IOL output low current (total)
mA
Rev. 3.00 May 15, 2007 Page 397 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Values Item Permissible output high current (per pin) Symbol Applicable Pins Test Condition -IOH All output pins
VCC = 2.7 V to 3.6 V
Min. --
Typ. -- --
Max. 2.0 0.2
Unit Notes mA
Other than above --
Permissible - IOH output high current (total)
All output pins
--
--
10.0
mA
Notes: 1. Pin states during current measurement.
Mode Active (high-speed) mode (IOPE1) Active (medium-speed) mode (IOPE2) Sleep mode Subactive mode Subsleep mode Watch mode Standby mode VCC VCC VCC VCC VCC Only on-chip timers operate Only CPU operates Only on-chip timers operate, CPU stops VCC VCC VCC RES Pin VCC Internal State Only CPU operates Other Pins VCC Oscillator Pins System clock oscillator: Crystal resonator Subclock oscillator: Pin X1 = GND
System clock oscillator: Crystal resonator Subclock oscillator: Crystal resonator System clock oscillator: Crystal resonator Subclock oscillator: Pin X1 = Crystal resonator
Only timer base VCC operates, CPU stops CPU and timers both VCC stop, SUBSTP = 1
2. Excludes current in pull-up MOS transistors and output buffers. 3. Used for the determination of user mode or boot mode when the reset is released. 4. When bits IRQ0S1 and IRQ0S0 are set to B'01 or B'10, and bits IRQ1S1 and IRQ1S0 are set to B'01 or B'10, the maximum value is given VCC + 0.3 (V).
Rev. 3.00 May 15, 2007 Page 398 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.2.3
AC Characteristics
Table 21.3 lists the control signal timing, table 21.4 lists the serial interface timing, table 21.5 lists the synchronous serial communication unit timing, and table 21.6 lists the I2C bus interface timing. Table 21.3 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Applicable Symbol Pins fOSC OSC1, OSC2 Values Test Condition
VCC = 2.7 V to 3.6 V (10-MHZ version) VCC = 1.8 V to 3.6 V (4-MHz version)
Item System clock oscillation frequency
Min. 4.0 2.0 100 238 1
Typ. -- -- -- -- -- -- -- --
Reference Max. Unit Figure 10.0 4.2 250 500 64 16 32 2.6 MHz Reference value s kHz Reference value tOSC s ns Figure 21.15 MHz
OSC clock (OSC) cycle time
tOSC
OSC1, OSC2
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
System clock () cycle time
tcyc
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
-- -- 0.3
On-chip oscillator oscillation frequency On-chip oscillator clock cycle time Subclock oscillator oscillation frequency Watch clock (W) cycle time Subclock (SUB) cycle time Instruction cycle time
tROSC
tROSC fW X1, X2
0.38 --
-- 32.768 or 38.4 30.5 or 26.0 -- --
3.3 --
tW tsubcyc
X1, X2
-- 1 2
-- 8 --
s tW tcyc tsubcyc
Figure 21.15 *
1
Rev. 3.00 May 15, 2007 Page 399 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Item Oscillation stabilization time
Applicable Symbol Pins trc OSC1, OSC2
Values Test Condition
Ceramic resonator (VCC = 2.2 V to 3.6 V) Ceramic resonator (Other than above) Crystal resonator (VCC = 2.7 V to 3.6 V) Crystal resonator (VCC = 2.2 V to 3.6 V) Other than above
Min. -- -- -- -- -- -- -- -- 40 95 --
Typ. 20 80 300 600 -- 15 -- 4 -- --
Reference Max. Unit Figure 45 -- 800 1000 50 25 2 -- -- -- s ns Figure 21.15 ns Figure 21.15 ms s s Figures 4.6 and 4.7 s Figure 21.28
On-chip oscillator X1, X2
At switching on
VCC = 2.2 V to 3.6 V
Other than above
External clock high width
tCPH
OSC1
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
X1 External clock low width tCPL OSC1
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
15.26 or -- 13.02 -- -- -- --
40 95 --
X1 External clock rising tCPr time OSC1
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
15.26 or -- 13.02 -- -- -- 10 24 55.0
s ns Figure 21.15
-- -- --
X1
ns
Rev. 3.00 May 15, 2007 Page 400 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Item External clock falling time
Applicable Symbol Pins tCPf OSC1
Values Test Condition
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
Min. -- -- --
Typ. -- -- -- -- -- --
Reference Max. Unit Figure 10 24 55.0 -- -- -- ns s tcyc tcyc Figure tsubcyc 21.17 Figure 2 21.16* ns Figure 21.15
X1 RES pin low width tREL RES
At switching on or other than below
trc + 20 x tcyc
Active mode or sleep 20 mode IRQ0, IRQ1, NMI, IRQAEC, ADTRG, FTCI, FTIOA, FTIOB, FTIOC, FTIOD
Input pin high width tIH
2
AEVL, AEVH
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
50 110 2
-- -- --
-- -- --
ns
Input pin low width
tIL
IRQ0, IRQ1, NMI, IRQAEC, ADTRG, FTCI, FTIOA, FTIOB, FTIOC, FTIOD
tcyc Figure tsubcyc 21.17
AEVL, AEVH
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
50 110
-- --
-- --
ns
Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2). 2. For details on the power-on reset characteristics, refer to table 21.10 and figure 21.26.
Rev. 3.00 May 15, 2007 Page 401 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Table 21.4 Serial Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values Item Input clock cycle Asynchronous Clock synchronous tSCKW tTXD tRXS tRXH Symbol tscyc Test Condition Min. 4 6 0.4 -- 400.0 400.0 Typ. -- -- -- -- -- -- Max. -- -- 0.6 1 -- -- Unit tcyc or tsubcyc Reference Figure Figure 21.18
Input clock pulse width Transmit data delay time (clock synchronous) Receive data setup time (clock synchronous) Receive data hold time (clock synchronous)
tscyc tcyc or tsubcyc ns ns
Figure 21.18 Figure 21.19 Figure 21.19 Figure 21.19
Rev. 3.00 May 15, 2007 Page 402 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Table 21.5 Synchronous Serial Communication Unit (SSU) Timing VCC = 1.8 V to 3.6 V, VSS = 0.0 V, output load = 100 pF, unless otherwise specified.
Applicable Test Pins Condition Values Min. Typ. Max. Unit Reference Figure
Item
Symbol
Clock cycle Clock high pulse width Clock low pulse width
Clock rising time Clock falling time
tsucyc tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR
SSCK SSCK SSCK SSCK
4 0.4 0.4

0.6 0.6 1 1.0 1 1.0 1
tcyc tsucyc tsucyc tcyc s tcyc s tcyc tcyc ns ns tcyc
Figures 21.20 to 21.24
Master Slave Master Slave
SSCK
Data input setup time Data input hold time SCS setup time SCS hold time Slave Slave
SSO SSI SSO SSI SCS SCS SSO SSI SSI SSI
1 1
1tcyc + 100 1tcyc + 100
Data output delay time Slave access time Slave out release time
1tcyc + ns 100 1tcyc + 100 ns
Rev. 3.00 May 15, 2007 Page 403 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Table 21.6 I2C Bus Interface Timing VCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified.
Test Item SCL input cycle time SCL input high width SCL input low width Falling time for SCL and SDA inputs Pulse width of spike on SCL and SDA to be suppressed SDA input bus-free time Start condition input hold time Repeated start condition input setup time Stop condition input setup time Data-input hold time Capacitive load of SCL and SDA Falling time of SCL and SDA output Symbol tSCL tSCLH tSCLL tSf tSP Condition Min. 3tcyc + 300 5tcyc + 300 -- -- Values Typ. -- -- -- -- Max. -- -- -- 300 1tcyc Unit ns ns ns ns ns 12tcyc + 600 -- Reference Figure Figure 21.25
tBUF tSTAH tSTAS
5tcyc 3tcyc 3tcyc
-- -- --
-- -- --
ns ns ns
tSTOS
3tcyc 1tcyc + 20 0 0 --
-- -- -- -- --
-- -- -- 400 300
ns ns ns pF ns
Data-input setup time tSDAS tSDAH Cb tSf
Rev. 3.00 May 15, 2007 Page 404 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.2.4
A/D Converter Characteristics
Table 21.7 lists the A/D converter characteristics. Table 21.7 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Applicable Symbol Pins AVCC AN0 to AN5 AVCC AVCC AVCC AN0 to AN5 AVCC = 3.0 V Values Test Condition Min. 1.8 -0.3 -- -- -- -- -- Typ. -- -- -- 600 -- -- -- Max. 3.6 AVCC + 0.3 1.0 -- 5 15.0 10.0 Unit V V mA A A pF k * *
2
Item
Notes *
1
Analog power AVCC supply voltage Analog input voltage AVIN
Analog power AIOPE supply current AISTOP1 AISTOP2 Analog input capacitance Permissible signal source impedance Resolution (data length) Nonlinearity error CAIN RAIN
Reference value
3
-- AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Subclock operating --
-- --
10 3.5
Bits LSB Other than subclock operation
-- --
-- --
5.5 5.5
Subactive or subsleep mode, conversion time = 31/W
Other than above Quantization error
-- --
-- --
7.5 0.5 LSB
*
4
Rev. 3.00 May 15, 2007 Page 405 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Item Absolute accuracy
Applicable Symbol Pins
Values Test Condition AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Subclock operating Min. -- -- -- Typ. -- -- -- Max. 4.0 6.0 6.0
Subactive or subsleep mode, conversion time = 31/W
Unit LSB
Notes
Other than above Conversion time AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V
-- 12.4
-- --
8.0 124 s
*
4
System clock oscillator is selected On-chip oscillator is selected Reference value (fROSC = 1 MHz) SUB = 38.4 kHz SUB = 32.8 kHz SUB = ROSC/32 Reference value (fROSC = 1 MHz)
31
62
124
-- -- --
807 945 992
-- -- --
Other than AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V
29.5
--
124
System clock oscillator is selected
31
62
124
On-chip oscillator is selected Reference value (fROSC = 1 MHz) SUB = 38.4 kHz SUB = 32.8 kHz SUB = ROSC/32 Reference value (fROSC = 1 MHz)
-- -- --
807 945 992
-- -- --
Notes: 1. Connect AVCC to VCC when the A/D converter is not used. 2. AISTOP1 is the current flowing through the ladder resistor while the A/D converter is idle. 3. AISTOP2 is the current flowing at a reset, in standby mode or watch mode, through the ladder resistor while the A/D converter is idle. 4. Conversion time is 29.5 s.
Rev. 3.00 May 15, 2007 Page 406 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.2.5
Comparator Characteristics
Table 21.8 shows the comparator characteristics. Table 21.8 Comparator Characteristics VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values Item Accuracy Test Condition 1LSB = VCC/30 Min. -- Typ. 1/2 Max. -- Unit LSB Notes
Comparing with internal resistor network
Conversion time External input reference voltage Internal resistance compare voltage Comparator input voltage Ladder resistance COMP0 and COMP1 pins VCref pin
-- 0.9 0.9 -0.3 --
-- -- -- -- 3
15
0.9 x VCC
s V
26/30 x VCC V AVCC + 0.3
V M
Reference value
--
21.2.6
Watchdog Timer Characteristics
Table 21.9 shows the watchdog timer characteristics. Table 21.9 Watchdog Timer Characteristics VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Applicable Symbol Pins tOVF Values Test Condition Min. 0.2 Typ. 0.4 Max. -- Unit s Notes *
Item On-chip oscillator overflow time
Note:
*
Indicates that the period from when the counter starts with 0 to when the counter reaches 255 and an internal reset occurs while the on-chip oscillator is selected.
Rev. 3.00 May 15, 2007 Page 407 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.2.7
Power-On Reset Circuit Characteristics
Table 21.10 lists the power-on reset circuit characteristics. Table 21.10 Power-On Reset Circuit Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = -20 to +75C (general specifications), Ta = -40 to +85C (wide temperature range specifications), unless otherwise specified.
Values Item Reset voltage Power supply rising time Reset count time Symbol Test Condition V_rst t_vtr Min. Typ. Max. Unit Notes
0.7Vcc 0.8Vcc 0.9Vcc V
The Vcc rising time should be shorter than half the RES rising time.
t_out
0.8 3.2
-- --
4.0 26.7
s
On-chip oscillator is selected (reference value)
Count start time
t_cr
Adjustable by the value of the external capacitor connected to the RES pin.
Pull-up resistance RP
60
100
--
k
Rev. 3.00 May 15, 2007 Page 408 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.2.8
Flash Memory Characteristics
Table 21.11 lists the flash memory characteristics. Table 21.11 Flash Memory Characteristics AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, VCC = 1.8 V to 3.6 V (operating voltage range in reading), VCC = 3.0 V to 3.6 V (operating voltage range in programming/erasing), Ta = 0 to +75C (operating temperature range in programming/erasing)
Test Item Programming time (per 128 bytes)* * * Erasing time (per block)* * *
136 124
Values Min. -- -- 1000 8 11 ** 100 8 12 ** Typ. 7 100 Max. 200 1200 Unit ms ms Times
Symbol Condition tP tE NWEC
Maximum programming count
10000 -- 9 * 10000 -- 9 * -- -- -- 30 200 10 -- -- -- -- -- -- -- -- -- -- 32 202 12 -- -- -- -- -- -- 1000
Data retention time Programming Wait time after setting SWE bit* Wait time after setting PSU bit* Wait time after setting P bit* *
14 1 1
tDRP x y z1 z2 z3 1n6 7 n 1000
10* 1 50 28
10
Years s s s s s s s s s s s Times
198
Additional8 programming 5 5 4 2 2 100 --
Wait time after clearing P bit*
1 1

1 1
Wait time after clearing PSU bit* Wait time after setting PV bit* Wait time after dummy write*
1 1
Wait time after clearing PV bit*
N
Wait time after clearing SWE bit*
Maximum programming count* * *
145
Rev. 3.00 May 15, 2007 Page 409 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics Values Min. 1 100 10 10 10 20 2 4 100 -- Typ. -- -- -- -- -- -- -- -- -- -- Max. -- -- 100 -- -- -- -- -- -- 120 Unit s s ms s s s s s s Times
Item Erase Wait time after setting SWE bit* Wait time after setting ESU bit* Wait time after setting E bit* * Wait time after clearing E bit*
16 1 1 1 1
Test Symbol Condition x y z
1 1
Wait time after clearing ESU bit* Wait time after setting EV bit* Wait time after dummy write*
1 1
Wait time after clearing EV bit* Maximum erasing count* * *
167
N
Wait time after clearing SWE bit*
Notes: 1. 2.
Make the time settings in accordance with the programming/erasing algorithms. The programming time for 128 bytes. (Indicates the total time for which the P bit in the flash memory control register 1 (FLMCR1) is set. The programming-verifying time is not included.) 3. The time required to erase one block. (Indicates the total time for which the E bit in the flash memory control register 1 (FLMCR1) is set. The erasing-verifying time is not included.) 4. Programming time maximum value (tP (max.)) = wait time after setting P bit (z) x maximum programming count (N) 5. Set the maximum programming count (N) according to the actual set values of z1, z2, and z3, so that it does not exceed the programming time maximum value (tP (max.)). The wait time after setting P bit (z1, z2) should be changed as follows according to the value of the programming count (n). Programming count (n) 1n6 z1 = 30 s 7 n 1000 z2 = 200 s 6. Erasing time maximum value (tE (max.)) = wait time after setting E bit (z) x maximum erasing count (N) 7. Set the maximum erasing count (N) according to the actual set value of (z), so that it does not exceed the erasing time maximum value (tE (max.)). 8. The minimum number of times in which all characteristics are guaranteed following reprogramming. (The guarantee covers the range from 1 to the minimum value.) 9. Reference value at 25C. (Guideline showing programming count over which functioning will be retained under normal circumstances.) 10. Data retention characteristics within the range indicated in the specifications, including the minimum programming count. 11. Applies to an operating voltage range when reading data of 2.7 to 3.6 V. 12. Applies to an operating voltage range when reading data of 1.8 to 3.6 V.
Rev. 3.00 May 15, 2007 Page 410 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.3
Absolute Maximum Ratings for Masked ROM Version
Table 21.12 lists the absolute maximum ratings. Table 21.12 Absolute Maximum Ratings
Item Power supply voltage Analog power supply voltage Input voltage Other than port B Port B Operating temperature Symbol VCC AVCC Vin AVin Topr Value -0.3 to +4.3 -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -20 to +75 (general specifications) -40 to +85 (wide temperature range specifications) Storage temperature Note: * Tstg -55 to +125 C Permanent damage may occur to the chip if absolute maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. Unit V V V V C Note *
Rev. 3.00 May 15, 2007 Page 411 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.4
21.4.1
Electrical Characteristics for Masked ROM Version
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
(1) System clock oscillator selected (10-MHz version)
fosc (MHz)
fW (kHz)
10.0
38.4 32.768
4.0 1.8 2.7 3.6 Vcc (V) 1.8 2.7 3.6 Vcc (V) * All operating modes * Refer to note Rosc/32 used (reference value)
* Active (high-speed) mode * Sleep (high-speed) mode 81.25
fW (kHz)
9.375
2.7 3.6 Vcc (V) 1.8 * All operating modes (2) System clock oscillator selected (4-MHz version)
fW (kHz)
38.4 32.768
fosc (MHz)
4.2 2.0 1.8 2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
2.7 3.6 Vcc (V) 1.8 * All operating modes * Refer to note Rosc/32 used (reference value)
fW (kHz)
81.25
9.375
2.7 3.6 Vcc (V) 1.8 * All operating modes Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation stabilization time has elapsed after switching on.
Figure 21.8 Power Supply Voltage and Oscillation Frequency Range (1)
Rev. 3.00 May 15, 2007 Page 412 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(3) On-chip oscillator selected Rosc used (reference value)
fW (kHz)
38.4 32.768
fosc (MHz)
2.6 0.3 1.8 2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 3.6 Vcc (V) * All operating modes * Refer to note Rosc/32 used (reference value)
fW (kHz)
81.25
9.375
1.8 2.7 3.6 Vcc (V) * All operating modes Note: * When using a resonator, hold the Vcc level in the range from 2.2 V to 3.6 V until the oscillation stabilization time has elapsed after switching on.
Figure 21.9 Power Supply Voltage and Oscillation Frequency Range (2)
Rev. 3.00 May 15, 2007 Page 413 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version) 10.0 38.4 32.768 19.2
SUB (kHz) (MHz)
16.384 9.6 8.192 4.8 4.096
4.0
1.8
2.7 3.6 Vcc (V)
1.8
2.7 3.6 Vcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
1250
62.5
(kHz)
Rosc/32 used (reference value) 81.25
SUB (kHz)
1.172 1.8 2.7 3.6 Vcc (V)
1.8
2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
Figure 21.10 Power Supply Voltage and Operating Frequency Range (1)
Rev. 3.00 May 15, 2007 Page 414 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(2) System clock oscillator selected (4-MHz version) 38.4 32.768
SUB (kHz) (MHz)
4.2 2.0
19.2 16.384 9.6 8.192 4.8 4.096
1.8 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 3.6 Vcc (V) * Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
525
(kHz)
Rosc/32 used (reference value) 31.25 81.25
SUB (kHz)
1.8 2.7 3.6 Vcc (V)
1.172 1.8 2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
Figure 21.11 Power Supply Voltage and Operating Frequency Range (2)
Rev. 3.00 May 15, 2007 Page 415 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(3) On-chip oscillator selected 38.4 32.768 19.2
SUB (kHz)
16.384 9.6 8.192 4.8 4.096
Rosc used (reference value)
(MHz)
2.6 0.3 1.8 2.7 3.6 Vcc (V) * Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 3.6 Vcc (V) * Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
Rosc used (reference value) 325
Rosc/32 used (reference value)
(kHz)
4.6875
SUB (kHz)
1.8 2.7 3.6 Vcc (V)
81.25
1.172 1.8 2.7 3.6 Vcc (V)
* Active (medium-speed) mode * Sleep (medium-speed) mode
* Subactive mode * Subsleep mode (other than CPU) * Watch mode (other than CPU)
Figure 21.12 Power Supply Voltage and Operating Frequency Range (3)
Rev. 3.00 May 15, 2007 Page 416 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(1) System clock oscillator selected (10-MHz version)
10.0
38.4
4.0
SUB (kHz)
(MHz)
32.768
1.8
2.7
3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 * All operating modes
Rosc/32 used (reference value)
3.6 AVcc (V)
81.25
SUB (kHz)
9.375
1.8 2.7 * All operating modes
(2) System clock oscillator selected (4-MHz version)
3.6 AVcc (V)
38.4
4.2
2.0
1.8 2.7 3.6 AVcc (V)
SUB (kHz)
(MHz)
32.768
* Active (high-speed) mode * Sleep (high-speed) mode
1.8 2.7 * All operating modes
3.6 AVcc (V)
Rosc/32 used (reference value)
81.25
SUB (kHz)
9.375
1.8 2.7 * All operating modes
3.6 AVcc (V)
Figure 21.13 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (1)
Rev. 3.00 May 15, 2007 Page 417 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
(3) On-chip oscillator selected Rosc used (reference value)
SUB (kHz)
38.4
32.768
(MHz)
2.6
0.3
1.8
2.7
3.6 AVcc (V)
1.8
2.7
3.6 AVcc (V)
* Active (high-speed) mode * Sleep (high-speed) mode
* All operating modes
Rosc/32 used (reference value)
SUB (kHz)
81.25
9.375
1.8 2.7 * All operating modes
3.6 AVcc (V)
Figure 21.14 Analog Power Supply Voltage and Operating Frequency Range of A/D Converter (2)
Rev. 3.00 May 15, 2007 Page 418 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.4.2
DC Characteristics
Table 21.13 lists the DC characteristics. Table 21.13 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values Item Input high voltage Symbol VIH Applicable Pins Test Condition RES, TEST, NMI, AEVL, AEVH, ADTRG, SCK3, IRQAEC IRQ0* , IRQ1*
3 3
Min. 0.9VCC
Typ. --
Max. VCC + 0.3
Unit V
Notes
0.9VCC 0.8VCC 0.9VCC 0.9VCC 0.8VCC
-- -- -- -- --
AVCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3
RXD3, IrRXD OSC1 X1 P10 to P12, P30 to P32, P82 to P84, P90 to P93, SSI, SSO, SSCK, SCS, FTCI, FTIOA, FTIOB, FTIOC, FTIOD, E7_0 to E7_2, SCL, SDA PB0 to PB5
0.8VCC
--
AVCC + 0.3
Rev. 3.00 May 15, 2007 Page 419 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Values Item Input low voltage Symbol VIL Applicable Pins Test Condition TEST, NMI, IRQ0, IRQ1, IRQAEC, AEVL, AEVH, ADTRG, SCK3 RXD3, IrRXD OSC1 X1 P10 to P12, P30 to P32, P82 to P84, P90 to P93, SCL, SDA, PB0 to PB5, SSI, SSO, SSCK, SCS, FTCI, FTIOA, FTIOB, FTIOC, FTIOD, E7_0 to E7_2 Output high voltage VOH P10 to P12, P30 to P32, P90 to P93 P82 to P84 Min. -0.3 Typ. -- Max. 0.1VCC Unit V Notes
-0.3 -0.3 -0.3 -0.3
-- -- -- --
0.2VCC 0.1VCC 0.1VCC 0.2VCC
-IOH = 1.0 mA VCC - 1.0 -- Vcc = 2.7 V to 3.6 V -IOH = 0.1 mA VCC - 0.3 --
-- -- -- -- 0.5
V
-IOH = 1.0 mA VCC - 1.0 -- VCC = 2.7 V to 3.6 V -IOH = 0.1 mA VCC - 0.3 -- -- --
Output low VOL voltage
P10 to P12, P30 to P32, P90 to P93 P82 to P84
IOL = 0.4 mA
V
IOL = 15 mA, -- Vcc = 2.7 V to 3.6 V IOL = 10 mA, -- Vcc = 2.2 V to 3.6 V IOL = 8 mA -- --
-- -- -- --
1.0 0.5 0.5 0.4
SCL, SDA
IOL = 3.0 mA
Rev. 3.00 May 15, 2007 Page 420 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Values Item Input/output leakage current Symbol Applicable Pins Test Condition | IIL | TEST, NMI, OSC1, X1, P10 to P12, P30 to P32, P82 to P84, P90 to P93, E7_0 to E7_2 PB0 to PB5 Pull-up MOS current -Ip P10 to P12, P30 to P32, P82 to P84, P90 to P93 All input pins except power supply pin VCC VIN = 0.5 V to VCC - 0.5 V Min. -- Typ. -- Max. 1.0 Unit A Notes
VIN = 0.5 V to AVCC - 0.5 V VCC = 3 V, VIN = 0 V
-- 30
-- --
1.0 180 A
Input capacitance
CIN
f = 1 MHz, VIN =0 V, Ta = 25C Active (highspeed) mode, VCC = 1.8 V, fOSC = 2 MHz Active (highspeed) mode, VCC = 3 V, fOSC = ROSC Active (highspeed) mode, VCC = 3 V, fOSC = 4.2 MHz Active (highspeed) mode, VCC = 3 V, fOSC = 10 MHz
--
--
15.0
pF
Active mode IOPE1 supply current
--
0.5
--
mA
Max. guideline = 1.1 x typ.* *
12
--
0.6
--
Max. guideline = 1.1 x typ.* *
12
Reference value
--
2.0
3.0
**
12
4-MHz version
--
4.5
6.8
**
12
10-MHz version
Rev. 3.00 May 15, 2007 Page 421 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Applicable Item Symbol Pins VCC Test Condition
Active (medium-speed) mode, VCC = 1.8 V, fOSC = 2 MHz, osc/64 Active (medium-speed) mode, VCC = 3 V, fOSC = 4.2 MHz, osc/64 Active (medium-speed) mode, VCC = 3 V, fOSC = 10 MHz, osc/64
Values Min. -- Typ. 0.1 Max. -- Unit Notes mA
Max. guideline = 1.1 x typ. * *
12
Active mode IOPE2 supply current
--
0.3
0.5
**
12
4-MHz version
--
0.5
0.7
**
12
10-MHz version
Sleep mode ISLEEP supply current
VCC
VCC = 1.8 V, fOSC = 2 MHz VCC = 3 V, fOSC = 4.2 MHz VCC = 3 V, fOSC = 10 MHz
-- -- -- --
0.3 1.0 1.8 4.0
-- 1.5 2.7 --
mA
Max. guideline = 1.1 x typ. * *
12
** ** A **
12
4-MHz version
12
10-MHz version
12
Subactive mode supply current
ISUB
VCC
VCC = 1.8 V, 32-kHz crystal resonator (SUB = W/2) VCC = 2.7 V, 32-kHz crystal resonator (SUB = W/8) VCC = 2.7 V, 32-kHz crystal resonator (SUB = W/2) VCC = 2.7 V, on-chip oscillator/32 (SUB = W = ROSC/32) VCC = 2.7 V, 32-kHz crystal resonator (SUB = W)
Reference value
--
3.6
--
**
12
Reference value
--
7.4
--
**
12
Reference value
--
40
--
**
12
Reference value
--
13
25
**
12
Rev. 3.00 May 15, 2007 Page 422 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Applicable Item Symbol Pins VCC Test Condition Min.
Values Typ. 3.1 Max. -- Unit Notes A **
12
Subsleep mode ISUBSP supply current
-- VCC = 2.7 V, 32-kHz crystal resonator (SUB = W/2) VCC = 2.7 V, on-chip oscillator/32 (SUB = W = ROSC/32) VCC = 2.7 V, 32-kHz crystal resonator (SUB = W) --
Reference value
30
--
**
12
Reference value
--
5.0
10.0
**
12
Watch mode supply current
IWATCH
VCC
VCC = 1.8 V, Ta = 25C, 32-kHz crystal resonator VCC = 2.7 V, 32-kHz crystal resonator
--
0.4
--
A
**
12
Reference value
--
1.5
5.0
**
12
Standby mode supply current
ISTBY
VCC
VCC = 3.0 V, Ta = 25C, 32-kHz crystal resonator not used 32-kHz crystal resonator not used
--
0.1
--
A
**
12
Reference value
-- 1.5
1.0 --
5.0 -- V
**
12
RAM data retaining voltage Permissible output low current (per pin) Permissible output low current (total)
VRAM
VCC
IOL
Output pins except port 8 Port 8
-- -- -- --
-- -- -- --
0.5 15.0 20.0 45.0
mA
IOL
Output pins except port 8 Port 8
mA
Rev. 3.00 May 15, 2007 Page 423 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Applicable Item Permissible output high current (per pin) Symbol Pins -IOH All output pins Test Condition
VCC = 2.7 V to 3.6 V
Values Min. -- Typ. -- -- -- Max. 2.0 0.2 10.0 mA Unit Notes mA
Other than above -- All output pins --
Permissible - IOH output high current (total)
Notes: 1. Pin states during current measurement.
Mode Active (high-speed) mode (IOPE1) Active (medium-speed) mode (IOPE2) Sleep mode Subactive mode Subsleep mode Watch mode Standby mode VCC VCC VCC VCC VCC Only on-chip timers operate Only CPU operates Only on-chip timers operate, CPU stops VCC VCC VCC RES Pin VCC Internal State Only CPU operates Other Pins VCC Oscillator Pins System clock oscillator: Crystal resonator Subclock oscillator: Pin X1 = GND
System clock oscillator: Crystal resonator Subclock oscillator: Crystal resonator System clock oscillator: Crystal resonator Subclock oscillator: Pin X1 = Crystal resonator
Only timer base VCC operates, CPU stops CPU and timers both VCC stop, SUBSTP = 1
2. Excludes current in pull-up MOS transistors and output buffers. 3. When bits IRQ0S1 and IRQ0S0 are set to B'01 or B'10, and bits IRQ1S1 and IRQ1S0 are set to B'01 or B'10, the maximum value is given VCC + 0.3 (V).
Rev. 3.00 May 15, 2007 Page 424 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.4.3
AC Characteristics
Table 21.14 lists the control signal timing, table 21.15 lists the serial interface timing, table 21.16 lists the synchronous serial communication unit timing, and table 21.17 lists the I2C bus interface timing. Table 21.14 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Applicable Item System clock oscillation frequency Symbol Pins fOSC OSC1, OSC2 Test Condition
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
Values Min. 4.0 2.0 100 238 1
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
Reference Max. 10.0 4.2 250 500 64 16 32 2.6 MHz Reference value s kHz Reference value tOSC s ns Figure 21.15 Unit Figure MHz
Typ. -- -- -- -- -- -- -- --
OSC clock (OSC) cycle time
tOSC
OSC1, OSC2
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
System clock () cycle time
tcyc
-- -- 0.3
On-chip oscillator oscillation frequency On-chip oscillator clock cycle time
tROSC
tROSC X1, X2
0.38 --
-- 32.768 or 38.4 30.5 or 26.0
3.3 --
Subclock oscillator fW oscillation frequency Watch clock (W) cycle time tW
X1, X2
--
--
s
Figure 21.15
Rev. 3.00 May 15, 2007 Page 425 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Item Subclock (SUB) cycle time Instruction cycle time Oscillation stabilization time
Applicable Symbol Pins tsubcyc
Values Test Condition Min. 1 2 Typ. -- -- 20 80 300 600 -- 15 -- Max. 8 -- 45 -- 800 1000 50 25 2 ms s s Unit tW tcyc tsubcyc s
Reference Figure *
1
trc
OSC1, OSC2
Ceramic resonator (VCC = 2.2 V to 3.6 V) Ceramic resonator (Other than above) Crystal resonator (VCC = 2.7 V to 3.6 V) Crystal resonator (VCC = 2.2 V to 3.6 V) Other than above
-- -- -- -- -- -- --
Figure 21.28
On-chip oscillator X1, X2
At switching on
VCC = 2.2 V to 3.6 V
Figures 4.6 and 4.7
Other than above External clock high tCPH width OSC1
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
-- 40 95 --
4 -- --
-- -- -- s ns Figure 21.15 ns Figure 21.15
X1 External clock low width tCPL OSC1
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
15.26 or -- 13.02 -- -- -- --
40 95 --
X1
15.26 or -- 13.02
s
Rev. 3.00 May 15, 2007 Page 426 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Item External clock rising time
Applicable Symbol Pins tCPr OSC1
Values Test Condition
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
Min. -- -- --
Typ. -- -- -- -- -- -- --
Max. 10 24 55.0 10 24 55.0 --
Unit ns
Reference Figure Figure 21.15
X1 External clock falling time tCPf OSC1
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
ns ns Figure 21.15
-- -- --
X1 RES pin low width tREL RES
At switching on or other than below
ns s tcyc Figure 2 21.16*
trc + 20 x tcyc
Active mode or sleep 20 mode
Input pin high width tIH
IRQ0, IRQ1, NMI, IRQAEC, ADTRG, FTCI, FTIOA, FTIOB, FTIOC, FTIOD AEVL, AEVH
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
2
--
--
tcyc Figure tsubcyc 21.17
50 110 2
-- -- --
-- -- --
ns
Input pin low width
tIL
IRQ0, IRQ1, NMI, IRQAEC, ADTRG, FTCI, FTIOA, FTIOB, FTIOC, FTIOD AEVL, AEVH
VCC = 2.7 V to 3.6 V (10-MHz version) VCC = 1.8 V to 3.6 V (4-MHz version)
tcyc Figure tsubcyc 21.17
50 110
-- --
-- --
ns
Notes: 1. Selected with the SA1 and SA0 bits in the system control register 2 (SYSCR2). 2. For details on the power-on reset characteristics, refer to table 21.21 and figure 21.26.
Rev. 3.00 May 15, 2007 Page 427 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Table 21.15 Serial Interface Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values Item Input clock cycle Asynchronous Clock synchronous tSCKW tTXD tRXS tRXH Symbol tscyc Test Condition Min. 4 6 0.4 -- 400.0 400.0 Typ. -- -- -- -- -- -- Max. -- -- 0.6 1 -- -- Unit tcyc or tsubcyc Reference Figure Figure 21.18
Input clock pulse width Transmit data delay time (clock synchronous) Receive data setup time (clock synchronous) Receive data hold time (clock synchronous)
tscyc tcyc or tsubcyc ns ns
Figure 21.18 Figure 21.19 Figure 21.19 Figure 21.19
Rev. 3.00 May 15, 2007 Page 428 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Table 21.16 Synchronous Serial Communication Unit (SSU) Timing VCC = 1.8 V to 3.6 V, VSS = 0.0 V, output load = 100 pF, unless otherwise specified.
Applicable Test Pins Condition Values Min. Typ. Max. Unit Reference Figure
Item
Symbol
Clock cycle Clock high pulse width Clock low pulse width
Clock rising time Clock falling time
tsucyc tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR
SSCK SSCK SSCK SSCK
4 0.4 0.4

0.6 0.6 1 1.0 1 1.0 1
tcyc tsucyc tsucyc tcyc s tcyc s tcyc tcyc ns ns tcyc
Figures 21.20 to 21.24
Master Slave Master Slave
SSCK
Data input setup time Data input hold time SCS setup time SCS hold time Slave Slave
SSO SSI SSO SSI SCS SCS SSO SSI SSI SSI
1 1
1tcyc + 100 1tcyc + 100
Data output delay time Slave access time Slave out release time
1tcyc + ns 100 1tcyc + 100 ns
Rev. 3.00 May 15, 2007 Page 429 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Table 21.17 I2C Bus Interface Timing VCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified.
Test Item SCL input cycle time SCL input high width SCL input low width Falling time for SCL and SDA inputs Pulse width of spike on SCL and SDA to be suppressed SDA input bus-free time Start condition input hold time Repeated start condition input setup time Stop condition input setup time Data-input hold time Capacitive load of SCL and SDA Falling time of SCL and SDA output Symbol tSCL tSCLH tSCLL tSf tSP Condition Min. 3tcyc + 300 5tcyc + 300 -- -- Values Typ. -- -- -- -- Max. -- -- -- 300 1tcyc Unit ns ns ns ns ns 12tcyc + 600 -- Reference Figure Figure 21.25
tBUF tSTAH tSTAS
5tcyc 3tcyc 3tcyc
-- -- --
-- -- --
ns ns ns
tSTOS
3tcyc 1tcyc + 20 0 0 --
-- -- -- -- --
-- -- -- 400 300
ns ns ns pF ns
Data-input setup time tSDAS tSDAH Cb tSf
Rev. 3.00 May 15, 2007 Page 430 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.4.4
A/D Converter Characteristics
Table 21.18 lists the A/D converter characteristics. Table 21.18 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Applicable Symbol Pins AVCC AN0 to AN5 AVCC AVCC AVCC = 3.0 V Values Test Condition Min. 1.8 -0.3 -- -- Typ. -- -- -- 600 Max. Unit 3.6 V Notes *
1
Item
Analog power AVCC supply voltage Analog input voltage AVIN
AVCC V + 0.3 1.0 -- mA A * Reference value *
3 2
Analog power AIOPE supply current AISTOP1
AISTOP2 Analog input capacitance Permissible signal source impedance Resolution (data length) Nonlinearity error CAIN RAIN
AVCC AN0 to AN5
-- -- --
-- -- --
5 15.0 10.0
A pF k
-- AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Subclock operating -- -- --
-- -- -- --
10 3.5 5.5 5.5
Bits LSB Other than subclock operation
Subactive or subsleep mode, conversion time = 31/W
Other than above Quantization error
-- --
-- --
7.5 0.5 LSB
*
4
Rev. 3.00 May 15, 2007 Page 431 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Applicable Item Absolute accuracy Symbol Pins Test Condition AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V AVCC = 2.0 V to 3.6 V VCC = 2.0 V to 3.6 V Subclock operating Min. -- -- --
Values Typ. -- -- -- Max. Unit 4.0 6.0 6.0
Subactive or subsleep mode, conversion time = 31/W
Notes
LSB
Other than above Conversion time AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V
-- 12.4
-- --
8.0 124 s
*
4
System clock oscillator is selected
31
62
124
On-chip oscillator is selected Reference value (fROSC = 1 MHz) SUB = 38.4 kHz SUB = 32.8 kHz SUB = ROSC/32 Reference value (fROSC = 1 MHz)
-- -- --
807 945 992
-- -- --
Other than AVCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V
29.5
--
124
System clock oscillator is selected
31
62
124
On-chip oscillator is selected Reference value (fROSC = 1 MHz) SUB = 38.4 kHz SUB = 32.8 kHz SUB = ROSC/32 Reference value (fROSC = 1 MHz)
-- -- --
807 945 992
-- -- --
Notes: 1. Connect AVCC to VCC when the A/D converter is not used. 2. AISTOP1 is the current flowing through the ladder resistor while the A/D converter is idle. 3. AISTOP2 is the current flowing at a reset, in standby mode or watch mode, through the ladder resistor while the A/D converter is idle. 4. Conversion time is 29.5 s.
Rev. 3.00 May 15, 2007 Page 432 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.4.5
Comparator Characteristics
Table 21.19 shows the comparator characteristics. Table 21.19 Comparator Characteristics VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Values Item Accuracy Test Condition 1LSB = VCC/30 Min. -- Typ. 1/2 Max. -- Unit LSB Notes
Comparing with internal resistor network
Conversion time External input reference voltage Internal resistance compare voltage Comparator input voltage Ladder resistance VCref pin
-- 0.9 0.9 COMP0 and COMP1 -0.3 pins --
-- -- -- -- 3
15
0.9 x VCC
s V
26/30 x VCC V AVCC + 0.3
V M
Reference value
--
21.4.6
Watchdog Timer Characteristics
Table 21.20 shows the watchdog timer characteristics. Table 21.20 Watchdog Timer Characteristics VCC = 1.8 V to 3.6 V, VSS = 0.0 V, unless otherwise specified.
Applicable Item On-chip oscillator overflow time Symbol Pins tOVF Test Condition Min. 0.2 Values Typ. 0.4 Max. -- Unit s Notes *
Note:
*
Indicates that the period from when the counter starts with 0 to when the counter reaches 255 and an internal reset occurs while the on-chip oscillator is selected.
Rev. 3.00 May 15, 2007 Page 433 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.4.7
Power-On Reset Circuit Characteristics
Table 21.21 lists the power-on reset circuit characteristics. Table 21.21 Power-On Reset Circuit Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = 0.0 V, Ta = -20 to +75C (general specifications), Ta = -40 to +85C (wide temperature range specifications), unless otherwise specified.
Values Item Reset voltage Power supply rising time Reset count time Symbol Test Condition V_rst t_vtr Min. Typ. Max. Unit Notes
0.7Vcc 0.8Vcc 0.9Vcc V
The Vcc rising time should be shorter than half the RES rising time.
t_out
0.8 3.2
-- --
4.0 26.7
s
On-chip oscillator is selected (reference value)
Count start time
t_cr
Adjustable by the value of the external capacitor connected to the RES pin.
Pull-up resistance RP
60
100
--
k
Rev. 3.00 May 15, 2007 Page 434 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.5
Operation Timing
Figures 21.15 to 21.26 show operation timings.
tOSC, tW
OSC1, X1
VIH VIL tCPH tCPr tCPL tCPf
Figure 21.15 Clock Input Timing
RES
VIL tREL
Figure 21.16 RES Low Width Timing
NMI, IRQ0, IRQ1, ADTRG, IRQAEC, AEVL, AEVH, FTCI, FTIOA to FTIOD
VIH VIL tIL tIH
Figure 21.17 Input Timing
tSCKW
SCK3
tScyc
Figure 21.18 SCK3 Input Clock Timing
Rev. 3.00 May 15, 2007 Page 435 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
tscyc
SCK3
VIH or VOH* VIL or VOL* tTXD
TXD3 (transmit data)
VOH* VOL* tRXS tRXH
RXD3 (receive data)
Note: * Output timing referenced levels Output high Output low VOH = 1/2Vcc + 0.2 V VOL = 0.8 V
Load conditions are shown in figure 21.27.
Figure 21.19 SCI3 Input/Output Timing in Clock Synchronous Mode
tHI
SSCK
VIH or VOH VIL or VOL tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 21.20 SSU Input/Output Timing in Clock Synchronous Mode
Rev. 3.00 May 15, 2007 Page 436 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
SCS (output)
VIH or VOH VIL or VOL tHI tFALL tRISE
SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tSU tH tOD tSUCYC
Figure 21.21 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 1)
VIH or VOH VIL or VOL tHI SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO SSO (output) tOH SSI (input) tSU tH tOD tSUCYC tFALL tRISE
SCS (output)
Figure 21.22 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 0)
Rev. 3.00 May 15, 2007 Page 437 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
SCS (input)
VIH or VOH VIL or VOL tLEAD tHI tFALL tRISE tLAG
SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tSU SSI (output) tSA tOH tOD tOR tH tSUCYC
Figure 21.23 SSU Input/Output Timing (Four-Line Bus Communication Mode, Slave, CPHS = 1)
SCS (input)
VIH or VOH VIL or VOL tLEAD tHI tFALL tRISE tLAG
SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO SSO (input) tSU SSI (output) tSA tOH tOD tOD tH tSUCYC
Figure 21.24 SSU Input/Output Timing (Four-Line Bus Communication Mode, Slave, CPHS = 0)
Rev. 3.00 May 15, 2007 Page 438 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
SDA tBUF
VIH VIL tSTAH tSCLH tSTAS tSP tSTOS
SCL P* S* tSf tSCLL tSCL Sr* tSr tSDAH tSDAS
P*
Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Repeated start condition
Figure 21.25 I2C Bus Interface Input/Output Timing
VCC t_vtr
v_rst RES
Internal reset
t_cr
t_out
Figure 21.26 Power-On Reset Circuit Reset Timing
Rev. 3.00 May 15, 2007 Page 439 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.6
Output Load Circuit
VCC
2.4 k
LSI output pin
30 pF
12 k
Figure 21.27 Output Load Condition
21.7
Recommended Resonators
(1) Recommended Crystal Resonators Frequency (MHz) 4.194304 10 Manufacturer NIHON DEMPA KOGYO CO., LTD. NIHON DEMPA KOGYO CO., LTD. Part No. NR-18 NR-18
(2) Recommended Ceramic Resonators Frequency (MHz) 2 Manufacturer Murata Manufacturing Co., Ltd. Part No. CSTCC2M00G53-B0 CSTCC2M00G56-B0 4.19 Murata Manufacturing Co., Ltd. CSTLS4M19G53-B0 CSTLS4M19G56-B0 10 Murata Manufacturing Co., Ltd. CSTLS10M0G53-B0 CSTLS10M0G56-B0
Figure 21.28 Recommended Resonators
Rev. 3.00 May 15, 2007 Page 440 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
21.8
Usage Note
The F-ZTAT and masked ROM versions satisfy the electrical characteristics shown in this manual, however actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on. When system evaluation testing is carried out using the F-ZTAT version, the same evaluation testing should also be conducted for the masked ROM version when changing over to that version.
Rev. 3.00 May 15, 2007 Page 441 of 516 REJ09B0152-0300
Section 21 Electrical Characteristics
Rev. 3.00 May 15, 2007 Page 442 of 516 REJ09B0152-0300
Appendix
Appendix
A.
A.1
Instruction Set
Instruction List
Condition Code
Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / ( ), < > Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Logical exclusive OR of the operands on both sides NOT (logical complement) Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7).
Rev. 3.00 May 15, 2007 Page 443 of 516 REJ09B0152-0300
Appendix
Condition Code Notation (cont)
Symbol
Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes
* 0 1 --
Rev. 3.00 May 15, 2007 Page 444 of 516 REJ09B0152-0300
Appendix
Table A.1
Instruction Set
1. Data Transfer Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
Mnemonic
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I #xx:8 Rd8
H
N
Z
V 0 0 0 0 0 0
C -- -- -- -- -- --
MOV
MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd
B B B B B B
2 2 2 4 8 2
---- ---- ---- ---- ---- ----
2 2 4 6 10 6
Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 @ERs Rd8 ERs32+1 ERs32 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd 4 8 2 Rs8 @(d:16, ERd) Rs8 @(d:24, ERd) ERd32-1 ERd32 Rs8 @ERd Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 #xx:16 Rd16 Rs16 Rd16 2 4 8 2 @ERs Rd16 @(d:16, ERs) Rd16 @(d:24, ERs) Rd16 @ERs Rd16 ERs32+2 @ERd32 @aa:16 Rd16 @aa:24 Rd16 Rs16 @ERd 4 8 Rs16 @(d:16, ERd) Rs16 @(d:24, ERd)
MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd
B B B B B B B 2
2 4 6
---- ---- ---- ---- ---- ---- ----
0 0 0 0 0 0 0
-- -- -- -- -- -- --
4 6 8 4 6 10 6
MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16, ERs), Rd MOV.W @(d:24, ERs), Rd MOV.W @ERs+, Rd
B B B W W W W W W 4 2
2 4 6
---- ---- ---- ---- ---- ---- ---- ---- ----
0 0 0 0 0 0 0 0 0
-- -- -- -- -- -- -- -- --
4 6 8 4 2 4 6 10 6
MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd)
W W W W W 2
4 6
---- ---- ---- ---- ----
0 0 0 0 0
-- -- -- -- --
6 8 4 6 10
Rev. 3.00 May 15, 2007 Page 445 of 516 REJ09B0152-0300
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I ERd32-2 ERd32 Rs16 @ERd Rs16 @aa:16 Rs16 @aa:24 #xx:32 ERd32 ERs32 ERd32
H
N
Z
V 0
C --
MOV
MOV.W Rs, @-ERd
W
2
----
6
MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd
W W L L L L L L 6 2 4 6 10 4
4 6
---- ---- ---- ---- ---- ---- ---- ----
0 0 0 0 0 0 0 0
-- -- -- -- -- -- -- --
6 8 6 2 8 10 14 10
@ERs ERd32 @(d:16, ERs) ERd32 @(d:24, ERs) ERd32 @ERs ERd32 ERs32+4 ERs32 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd 6 10 4 ERs32 @(d:16, ERd) ERs32 @(d:24, ERd) ERd32-4 ERd32 ERs32 @ERd ERs32 @aa:16 ERs32 @aa:24 2 @SP Rn16 SP+2 SP 4 @SP ERn32 SP+4 SP 2 SP-2 SP Rn16 @SP 4 SP-4 SP ERn32 @SP
MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd
L L L L L L 4
6 8
---- ---- ---- ---- ---- ----
0 0 0 0 0 0
-- -- -- -- -- --
10 12 8 10 14 10
MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP POP.W Rn
L L W
6 8
---- ---- ----
0 0 0
-- -- --
10 12 6
POP.L ERn
L
----
0
--
10
PUSH
PUSH.W Rn
W
----
0
--
6
PUSH.L ERn
L
----
0
--
10
MOVFPE MOVFPE @aa:16, Rd
B
4
Cannot be used in this LSI
Cannot be used in this LSI Cannot be used in this LSI
MOVTPE MOVTPE Rs, @aa:16
B
4
Cannot be used in this LSI
Rev. 3.00 May 15, 2007 Page 446 of 516 REJ09B0152-0300
Appendix
2. Arithmetic Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Mnemonic
Operand Size
Condition Code Operation
@(d, ERn)
I Rd8+#xx:8 Rd8 -- --
H
N
Z
V
C

ADD
ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd
B B W W L
2 2 4 2 6
2 2 4 2 6
Rd8+Rs8 Rd8 Rd16+#xx:16 Rd16 Rd16+Rs16 Rd16 ERd32+#xx:32 ERd32 ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8
-- (1) -- (1) -- (2)
ADD.L ERs, ERd
L
2
-- (2)
2
ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC INC.B Rd INC.W #1, Rd INC.W #2, Rd INC.L #1, ERd INC.L #2, ERd DAA DAA Rd
B B L L L B W W L L B
2 2 2 2 2 2 2 2 2 2 2
-- --
(3) (3)
2 2 2 2 2 2 2 2 2 2 2
Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 Rd16+1 Rd16 Rd16+2 Rd16 ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8
------------ ------------ ------------
---- ---- ---- ---- ---- -- *
-- -- -- -- --
*
SUB
SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd
B W W L L B B L L L B W W 2 6 4
2
--

Rd8-Rs8 Rd8 Rd16-#xx:16 Rd16 Rd16-Rs16 Rd16 ERd32-#xx:32 ERd32 ERd32-ERs32 ERd32 Rd8-#xx:8-C Rd8 Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 Rd16-1 Rd16 Rd16-2 Rd16
2 4 2 6 2 2 2 2 2 2 2 2 2
-- (1) -- (1) -- (2) -- (2) -- --
2
2
SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd
(3) (3)
2 2 2 2 2 2 2
------------ ------------ ------------ ---- ---- ----
-- -- --
Rev. 3.00 May 15, 2007 Page 447 of 516 REJ09B0152-0300
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8
H
N
Z
V
C -- -- --
DEC
DEC.L #1, ERd DEC.L #2, ERd
L L B
2 2 2
---- ---- -- *
2 2 2
DAS
DAS.Rd
*
MULXU MULXU. B Rs, Rd
B
2
Rd8 x Rs8 Rd16 (unsigned multiplication) Rd16 x Rs16 ERd32 (unsigned multiplication) Rd8 x Rs8 Rd16 (signed multiplication) Rd16 x Rs16 ERd32 (signed multiplication) Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division)
------------
14
MULXU. W Rs, ERd
W
2
------------
22
MULXS MULXS. B Rs, Rd
B
4
----
----
16
MULXS. W Rs, ERd
W
4
----
----
24
DIVXU DIVXU. B Rs, Rd
B
2
-- -- (6) (7) -- --
14
DIVXU. W Rs, ERd
W
2
ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (unsigned division)
-- -- (6) (7) -- --
22
DIVXS DIVXS. B Rs, Rd
B
4
Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division)
-- -- (8) (7) -- --
16
DIVXS. W Rs, ERd
W
4
ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed division)
-- -- (8) (7) -- --
24

CMP
CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd
B B W W L L
2 2 4 2 6 2
Rd8-#xx:8 Rd8-Rs8 Rd16-#xx:16 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32
-- --
2 2 4 2 4 2
-- (1) -- (1) -- (2) -- (2)
Rev. 3.00 May 15, 2007 Page 448 of 516 REJ09B0152-0300
Appendix
Addressing Mode and Instruction Length (bytes)
No. of States*1
@-ERn/@ERn+
Mnemonic
Operand Size
Condition Code Operation
@(d, ERn)
I 0-Rd8 Rd8 0-Rd16 Rd16 0-ERd32 ERd32 0 ( of Rd16) 0 ( of ERd32) ( of Rd16) ( of Rd16) ( of ERd32) ( of ERd32) -- -- --
H
N
Z
V
C

NEG
NEG.B Rd NEG.W Rd NEG.L ERd
B W L W
2 2 2 2
2 2 2 2
EXTU
EXTU.W Rd
----
0
0
--
EXTU.L ERd
L
2
----
0
0
--
2
EXTS
EXTS.W Rd
W
2
----
0
--
2
EXTS.L ERd
L
2
----
0
--
2
Rev. 3.00 May 15, 2007 Page 449 of 516 REJ09B0152-0300
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Appendix
3. Logic Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I Rd8#xx:8 Rd8
H
N
Z
V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
AND
AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd
B B W W L L B B W W L L B B W W L L B W L
2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2
Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 Rd16#xx:16 Rd16 Rd16Rs16 Rd16 ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8 Rd8 Rd16 Rd16 Rd32 Rd32
OR
OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd
XOR
XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd
NOT
NOT.B Rd NOT.W Rd NOT.L ERd
Rev. 3.00 May 15, 2007 Page 450 of 516 REJ09B0152-0300
Appendix
4. Shift Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I C MSB LSB C MSB C MSB 0 MSB C MSB LSB C MSB C MSB LSB C MSB LSB LSB LSB LSB C LSB 0 0
H
N
Z
V
C
SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd
B W L B W L B W L B W L B W L B W L B W L B W L
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rev. 3.00 May 15, 2007 Page 451 of 516 REJ09B0152-0300
Appendix
5. Bit-Manipulation Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I (#xx:3 of Rd8) 1
H
N
Z
V
C
BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT BNOT #xx:3, Rd
B B B B B B B B B B B B B
2 4 4 2 4 4 2 4 4 2 4 4 2
------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
2 8 8 2 8 8 2 8 8 2 8 8 2
(#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) (#xx:3 of Rd8) (#xx:3 of @ERd) (#xx:3 of @ERd) (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) (Rn8 of @ERd) (Rn8 of @ERd) (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8) Z
BNOT #xx:3, @ERd
B
4
------------
8
BNOT #xx:3, @aa:8
B
4
------------
8
BNOT Rn, Rd
B
2
------------
2
BNOT Rn, @ERd
B
4
------------
8
BNOT Rn, @aa:8
B
4
------------
8
BTST
BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8
B B B B B B B
2 4 4 2 4 4 2
------ ------ ------ ------ ------ ------
---- ---- ---- ---- ---- ----
2 6 6 2 6 6 2
(#xx:3 of @ERd) Z (#xx:3 of @aa:8) Z (Rn8 of @Rd8) Z (Rn8 of @ERd) Z (Rn8 of @aa:8) Z (#xx:3 of Rd8) C
BLD
BLD #xx:3, Rd
----------
Rev. 3.00 May 15, 2007 Page 452 of 516 REJ09B0152-0300
Appendix
Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation Advanced 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I (#xx:3 of @ERd) C
H
N
Z
V
C
BLD
BLD #xx:3, @ERd BLD #xx:3, @aa:8
B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 2 2 2 2 2 2 2 2
4 4
---------- ---------- ---------- ---------- ----------
(#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd) C
BILD
BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8
4 4
(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C (#xx:3 of @ERd24)
BST
BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8
------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ----------
4 4
C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd24)
BIST
BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8
4 4
C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C
BAND BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8
4 4
C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C
4 4
C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C
4 4
C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C
4 4
C (#xx:3 of @aa:8) C C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C
4 4
C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C
4 4
C (#xx:3 of @aa:8) C
Rev. 3.00 May 15, 2007 Page 453 of 516 REJ09B0152-0300
Appendix
6. Branching Instructions
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Mnemonic
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
@(d, ERn)
@ERn
@aa
Branch Condition If condition is true then PC PC+d else next; C Z = 0 Never Always
#xx
Rn
--
I
H
N
Z
V
C
Bcc
BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
------------ ------------ ------------ ------------ ------------ ------------
4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6
C Z = 1
------------ ------------
C=0
------------ ------------
C=1
------------ ------------
Z=0
------------ ------------
Z=1
------------ ------------
V=0
------------ ------------
V=1
------------ ------------
N=0
------------ ------------
N=1
------------ ------------
NV = 0
------------ ------------
NV = 1
------------ ------------
Z (NV) = 0
------------ ------------
Z (NV) = 1
------------ ------------
Rev. 3.00 May 15, 2007 Page 454 of 516 REJ09B0152-0300
Appendix
Addressing Mode and Instruction Length (bytes)
@-ERn/@ERn+
No. of States*1
Operand Size
Condition Code Operation
Advanced @(d, PC) Normal @@aa
Mnemonic
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I PC ERn
H
N
Z
V
C
JMP
JMP @ERn JMP @aa:24 JMP @@aa:8
-- -- -- --
2 4 2 2
------------ ------------ ------------ ------------ 8 6
4 6 10 8
PC aa:24 PC @aa:8 PC @-SP PC PC+d:8 PC @-SP PC PC+d:16 PC @-SP PC ERn PC @-SP PC aa:24 PC @-SP PC @aa:8 2 PC @SP+
BSR
BSR d:8
BSR d:16
--
4
------------
8
10
JSR
JSR @ERn
--
2
------------
6
8
JSR @aa:24
--
4
------------
8
10
JSR @@aa:8
--
2
------------
8
12
RTS
RTS
--
------------
8
10
Rev. 3.00 May 15, 2007 Page 455 of 516 REJ09B0152-0300
Appendix
7. System Control Instructions
Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1
Mnemonic
Operand Size
Condition Code Operation Advanced 16 10 2 2 2 6 8 12 8 8 10 2 6 8 12 8 8 10 2 2 2 2 @(d, PC) Normal 14 @@aa
@(d, ERn)
@ERn
@aa
#xx
Rn
--
I 1 CCR @-SP PC
H
N
Z
V
C
TRAPA TRAPA #x:2
--
2 PC @-SP
----------

RTE
RTE
--
CCR @SP+ PC @SP+
SLEEP SLEEP
--
Transition to powerdown state
--
----------
LDC
LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR
B B W W W W
2 2 4 6 10 4
#xx:8 CCR Rs8 CCR @ERs CCR @(d:16, ERs) CCR @(d:24, ERs) CCR @ERs CCR ERs32+2 ERs32 6 8 2 4 6 10 4 @aa:16 CCR @aa:24 CCR CCR Rd8 CCR @ERd CCR @(d:16, ERd) CCR @(d:24, ERd) ERd32-2 ERd32 CCR @ERd 6 8 CCR @aa:16 CCR @aa:24 CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 PC PC+2

LDC @aa:16, CCR LDC @aa:24, CCR STC STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd
W W B W W W W
-- -- -- -- --
---------- ---------- ---------- ---------- ----------
STC CCR, @aa:16 STC CCR, @aa:24 ANDC ANDC #xx:8, CCR ORC ORC #xx:8, CCR
W W B B B -- 2 2 2
-- --
---------- ----------
XORC XORC #xx:8, CCR NOP NOP
--
----------
Rev. 3.00 May 15, 2007 Page 456 of 516 REJ09B0152-0300

Appendix
8. Block Data Transfer Instructions
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Operand Size
Condition Code Operation
Mnemonic
@(d, ERn)
I
H
N
Z
V
C
EEPMOV
EEPMOV. B
--
4 if R4L 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L until else next R4L=0
------------
8+4n*2
EEPMOV. W
--
4 if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until else next R4=0
------------
8+4n*2
Notes: 1. The number of states in cases where the instruction code and its operands are located in on-chip memory is shown here. For other cases, see appendix A.3, Number of Execution States. 2. n is the value set in register R4L or R4. (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (3) Retains its previous value when the result is zero; otherwise cleared to 0. (4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value. (5) The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev. 3.00 May 15, 2007 Page 457 of 516 REJ09B0152-0300
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
A.2
Appendix
Table A.2
Instruction code: Instruction when most significant bit of BH is 1.
4 ORC ADD CMP SUBX MOV XORC ANDC LDC Table A-2 (2) ADDX Table A-2 (2) Table A-2 (2) Table A-2 (2) 5 6 7 8 9 A B C D E F Table A-2 (2) Table A-2 (2)
REJ09B0152-0300
1st byte AH AL
2nd byte BH BL
Instruction when most significant bit of BH is 0.
AL 2 LDC 3
AH
0
1
0
NOP
Table A-2 (2) OR.B SUB XOR.B AND.B Table A-2 (2)
STC
Operation Code Map
1
Table A-2 Table A-2 Table A-2 Table A-2 (2) (2) (2) (2)
2 MOV.B
Rev. 3.00 May 15, 2007 Page 458 of 516
Operation Code Map (1)
3
4 BVS
BRA
BRN
BHI
BLS
BCC
BCS
BNE
BEQ
BVC
BPL
BMI
BGE
BLT
BGT
BLE
5 BST OR BTST BOR MOV BIOR ADD BIXOR BIAND BILD Table A-2 (2) BXOR BAND BIST BLD XOR AND
MULXU
DIVXU
MULXU
DIVXU
RTS
BSR
RTE
TRAPA
Table A-2 (2) JMP
BSR MOV
JSR
6
BSET
BNOT
BCLR
7
Table A-2 EEPMOV (2)
Table A-2 (3)
8
9 ADDX
A CMP
B
SUBX
C
OR
D
XOR
E
AND
F
MOV
Table A.2
Instruction code:
1st byte AH AL
2nd byte BH BL
BH AH AL 1 LDC/STC SLEEP ADD INC ADDS MOV SHLL SHAL SHAR ROTL ROTR EXTU EXTU NEG SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG SUB DEC DEC SUBS CMP BRN ADD ADD CMP SUB OR CMP SUB OR BHI BLS BCC BCS XOR XOR BNE AND AND BEQ BVC BVS BPL BMI BGE BLT DEC EXTS INC INC Table A-2 Table A-2 (3) (3) 2 3 4 5 6 7 8 9 A B C D
0
E
F Table A-2 (3)
01
MOV
0A
INC
0B
ADDS
INC
Operation Code Map (2)
0F
DAA
10
SHLL
11
SHLR
12
ROTXL
13
ROTXR
17
NOT
EXTS
1A
DEC
1B
SUBS
DEC
1F
DAS
58
BRA
BGT
BLE
79
MOV
7A
MOV
Appendix
Rev. 3.00 May 15, 2007 Page 459 of 516
REJ09B0152-0300
Appendix
Table A.2
REJ09B0152-0300
Instruction code: Instruction when most significant bit of DH is 1.
1st byte AH AL Instruction when most significant bit of DH is 0.
2nd byte BH BL
3rd byte CH CL 4th byte DH DL
CL 1 2 3 4 5 6 7 8 9 A B C D E F
AH ALBH BLCH LDC STC MULXS STC LDC LDC
0
01406
LDC STC STC
Rev. 3.00 May 15, 2007 Page 460 of 516
Operation Code Map (3)
01C05
MULXS
01D05
DIVXS
DIVXS
01F06
OR
XOR
AND
7Cr06 *1 BTST BOR BTST BIOR BNOT BIST BNOT BCLR BCLR BIXOR BIAND BILD BST BXOR BAND BLD
7Cr07 *1
7Dr06 *1
BSET
7Dr07 *1
BSET
7Eaa6 *2 BTST BOR BTST BIOR BNOT BCLR BIXOR BIAND BXOR BAND
7Eaa7 *2
BLD BILD BST BIST
7Faa6 *2
BSET
7Faa7 *2 BNOT BCLR
BSET
Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix
A.3
Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle. The total number of states required for execution of an instruction can be calculated by the following expression:
Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8
L=M=N=0
Rev. 3.00 May 15, 2007 Page 461 of 516 REJ09B0152-0300
Appendix
Table A.3
Number of Cycles in Each Instruction
Access Location On-Chip Memory SI SJ SK SL SM SN 2 or 3* -- 1 2 On-Chip Peripheral Module --
Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: *
Depends on which on-chip peripheral module is accessed. See section 20.1, Register Addresses (Address Order).
Rev. 3.00 May 15, 2007 Page 462 of 516 REJ09B0152-0300
Appendix
Table A.4
Number of Cycles in Each Instruction
Instruction Fetch I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDX ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8
Rev. 3.00 May 15, 2007 Page 463 of 516 REJ09B0152-0300
Appendix
Instruction Fetch I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic Bcc BLT d:8 BGT d:8 BLE d:8 BRA d:16(BT d:16) BRN d:16(BF d:16) BHI d:16 BLS d:16 BCC d:16(BHS d:16) BCS d:16(BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8
Rev. 3.00 May 15, 2007 Page 464 of 516 REJ09B0152-0300
Appendix
Instruction Mnemonic BIOR BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR BSR d:8 BSR d:16 BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8
Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 1 2 2
Branch Stack Addr. Read Operation J K
Byte Data Access L
Word Data Access M
Internal Operation N
1 1
2 2
1 1
1 1
2 2
2 2
1 1
2 2
2 2 1 1 2
2 2
Rev. 3.00 May 15, 2007 Page 465 of 516 REJ09B0152-0300
Appendix
Instruction Fetch I 1 2 2 1 2 2 1 2 2 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 2n+2*1 2n+2*1 12 20 12 20 1 1 1 1 1 1 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd
Rev. 3.00 May 15, 2007 Page 466 of 516 REJ09B0152-0300
Appendix
Instruction Mnemonic INC INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR LDC@ERs, CCR LDC@(d:16, ERs), CCR LDC@(d:24,ERs), CCR LDC@ERs+, CCR LDC@aa:16, CCR LDC@aa:24, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @Erd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8
Instruction Fetch I 1 1 1 2 2 2 2 2 2 1 1 2 3 5 2 3 4 1 1 1 2 4 1 1 2 3 1 2 4 1 1
Branch Stack Addr. Read Operation J K
Byte Data Access L
Word Data Access M
Internal Operation N
2 1 1 1 1 1 2 2
1 1 1 1 1 1 2
1 1 1 1 1 1 1 1 1 1 1 1 2 2
Rev. 3.00 May 15, 2007 Page 467 of 516 REJ09B0152-0300
Appendix
Instruction Fetch I 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4
2
Instruction Mnemonic MOV MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16,ERs), Rd MOV.W @(d:24,ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16,ERd) MOV.W Rs, @(d:24,ERd) MOV.W Rs, @-ERd MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16,ERs), ERd MOV.L @(d:24,ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs,@ERd MOV.L ERs, @(d:16,ERd) MOV.L ERs, @(d:24,ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 MOVFPE MOVTPE MOVFPE @aa:16, Rd* MOVTPE Rs,@aa:16*2
Branch Stack Addr. Read Operation J K
Byte Data Access L 1 1
Word Data Access M
Internal Operation N
1 1 1 1 1 1 1 1 1 1 1 1 2 2
2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2
2 2
Rev. 3.00 May 15, 2007 Page 468 of 516 REJ09B0152-0300
Appendix
Instruction Mnemonic MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd ORC POP ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd
Instruction Fetch I 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 1 2 1 2 1 1 1 1 1 1 1 1 1
Branch Stack Addr. Read Operation J K
Byte Data Access L
Word Data Access M
Internal Operation N 12 20 12 20
1 2 1 2
2 2 2 2
Rev. 3.00 May 15, 2007 Page 469 of 516 REJ09B0152-0300
Appendix
Instruction Fetch I 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 5 2 3 4 1 2 1 3 1 1 1 1 1 1 1 1 2 2 1 2 2 Branch Stack Addr. Read Operation J K Byte Data Access L Word Data Access M Internal Operation N
Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTS SHAL RTE RTS SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP STC SLEEP STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16,ERd) STC CCR, @(d:24,ERd) STC CCR,@-ERd STC CCR, @aa:16 STC CCR, @aa:24 SUB SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS SUBS #1/2/4, ERd
Rev. 3.00 May 15, 2007 Page 470 of 516 REJ09B0152-0300
Appendix
Instruction Mnemonic SUBX SUBX #xx:8, Rd SUBX. Rs, Rd TRAPA XOR TRAPA #xx:2 XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR
Instruction Fetch I 1 1 2 1 1 2 1 3 2 1
Branch Stack Addr. Read Operation J K
Byte Data Access L
Word Data Access M
Internal Operation N
1
2
Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2. It cannot be used in this LSI.
Rev. 3.00 May 15, 2007 Page 471 of 516 REJ09B0152-0300
Appendix
A.4
Combinations of Instructions and Addressing Modes Combinations of Instructions and Addressing Modes
Addressing Mode
@ERn+/@ERn @(d:16.ERn) @(d:24.ERn)
Table A.5
@(d:8.PC)
Functions
Instructions
@ERn #xx
@(d:16.PC)
@@aa:8
@aa:16
@aa:24
@aa:8
Rn
Data transfer instructions
MOV POP, PUSH MOVFPE, MOVTPE ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS
BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
B -- -- -- -- -- -- -- -- --
BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
-- WL -- -- -- -- -- -- -- --
Arithmetic operations
BWL BWL WL BWL B -- -- -- -- B L BWL B BW
-- -- -- -- -- --
BWL WL BWL BWL BWL B -- -- -- -- -- -- B B -- -- --
-- -- -- -- -- B -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- W W -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
Logical operations Shift operations Bit manipulations Branching instructions
AND, OR, XOR NOT
BCC, BSR JMP, JSR RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP
-- -- -- -- -- -- B -- B -- --
System control instructions
-- -- -- W W -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- BW -- --
Block data transfer instructions
Rev. 3.00 May 15, 2007 Page 472 of 516 REJ09B0152-0300
--
Appendix
B.
B.1
I/O Ports
I/O Port Block Diagrams
SBY
PUCR12
VCC VCC
PMR15 (IRQAEC)
P12 PDR12
VSS
PCR12
Internal data bus
AEC module
IRQAEC
PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1
ECPWM AECPWM
Figure B.1 (a) Port 1 Block Diagram (P12)
Rev. 3.00 May 15, 2007 Page 473 of 516 REJ09B0152-0300
Appendix
SBY
PUCR11
VCC VCC
PMR14 (FTCI) PMR13 (AEVL)
VSS
PFCR (IRQ1S1, IRQ1S0) PDR11
PCR11
Internal data bus
AEC module
P11
AEVL
Timer W module
FTCI
IRQ1
PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 PFCR : Pin function control register
Figure B.1 (b) Port 1 Block Diagram (P11)
Rev. 3.00 May 15, 2007 Page 474 of 516 REJ09B0152-0300
Appendix
Timer W
SBY
PUCR10 PMR12 (CLKOUT) PMR11 (TMOW) PMR10 (AEVH) P12 PDR10
Internal data bus
Output control signal A
VCC VCC
VSS
PCR10
FTIOA WATCH
AEC module
AEVH
RTC module
TMOW
PDR1: PCR1: PMR1: PUCR1: WATCH: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Watch mode CLKOUT osc, osc/2, osc/4
Figure B.1 (c) Port 1 Block Diagram (P10)
Rev. 3.00 May 15, 2007 Page 475 of 516 REJ09B0152-0300
Appendix
SBY
PUCR32 SPCR (SCINV1)
VCC VCC
Internal data bus
SPCR (SPC3)
SCI3 module TXD3/IrTXD
P32 PDR32
VSS
PCR32
PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 SPCR: Serial port control register
Figure B.2 (a) Port 3 Block Diagram (P32)
Rev. 3.00 May 15, 2007 Page 476 of 516 REJ09B0152-0300
Appendix
SCI3 module SBY
RE3 RXD3/IrRXD
PUCR31
VCC VCC
P31 PDR31
VSS
PCR31
PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 SPCR: Serial port control register
SPCR (SCINV0)
Figure B.2 (b) Port 3 Block Diagram (P31)
Rev. 3.00 May 15, 2007 Page 477 of 516 REJ09B0152-0300
Internal data bus
Appendix
SBY
SCI3 module SCKIE3 SCKOE3 SCKO3
PUCR30
SCKI3
PMR30 (VCref)
VCC
PFCR (IRQ0S1, IRQ0S0)
P30 PDR30
VSS
PCR30
Internal data bus
VCC
Comparator VCref IRQ0 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3
Figure B.2 (c) Port 3 Block Diagram (P30)
Rev. 3.00 May 15, 2007 Page 478 of 516 REJ09B0152-0300
Appendix
SBY
PUCR8n
Timer W Output control signals B to D
VCC
P8n
PDR8n
VSS
PCR8n
Internal data bus
FTIOB to FTIOD WATCH
PDR8: Port data register 8 PCR8: Port control register 8 PUCR8: Port pull-up control register 8 WATCH: Watch mode n = 4 to 2
Figure B.3 (a) Port 8 Block Diagram (P84 to P82)
Rev. 3.00 May 15, 2007 Page 479 of 516 REJ09B0152-0300
Appendix
SBY
PUCR93
SSU SSI output control
VCC
PODR93
SSI input control SSI NMOS open-drain output control
P93
PFCR (IRQ1S1, IRQ1S0)
PDR93
VSS
PCR93
Internal data bus
SSI output SSI input IRQ1
PDR9: Port data register 9 PCR9: Port control register 9 PODR9: Port open-drain control register 9 PUCR9: Port pull-up control register 9
Note: When the SSUS bit in PFCR is 1, the SSI pin is switched to the SCS pin.
Figure B.4 (a) Port 9 Block Diagram (P93)
Rev. 3.00 May 15, 2007 Page 480 of 516 REJ09B0152-0300
Appendix
SBY
PUCR92
SSU SSO output control
VCC
PODR92
Internal data bus
SSO input control SSO NMOS open-drain output control
P92
PFCR (IRQ0S1, IRQ0S0)
PDR92
VSS
PCR92
SSO output SSO input IRQ0 PDR9: Port data register 9 PCR9: Port control register 9 PODR9: Port open-drain control register 9 PUCR9: Port pull-up control register 9 Note: When the SSUS bit in PFCR is 1, the SSO pin is switched to the SSCK pin.
Figure B.4 (b) Port 9 Block Diagram (P92)
Rev. 3.00 May 15, 2007 Page 481 of 516 REJ09B0152-0300
Appendix
SBY
PUCR91
SSU SSCK output control
VCC
PODR91 P91 PDR91
VSS
PCR91
Internal data bus
SSCK input control SSCK NMOS open-drain output control
SSCK output SSCK input IIC2 bus module
ICE SDAO SDAI
VSS
PDR9: Port data register 9 PCR9: Port control register 9 PODR9: Port open-drain control register 9 PUCR9: Port pull-up control register 9
Note:Priority: SSU pin > IIC2 pin > P91 When the SSUS bit in PFCR is 1, the SSCK pin is switched to the SSO pin.
Figure B.4 (c) Port 9 Block Diagram (P91)
Rev. 3.00 May 15, 2007 Page 482 of 516 REJ09B0152-0300
Appendix
SBY
PUCR90
SSU SCS output control
VCC
PODR90 P90 PDR90
VSS
PCR90
Internal data bus
SCS input control SCS NMOS open-drain output control
SCS output SCS input IIC2 bus module
ICE SCLO SCLI
VSS
PDR9: Port data register 9 PCR9: Port control register 9 PODR9: Port open-drain control register 9 PUCR9: Port pull-up control register 9
Note: Priority: SSU pin > IIC2 pin > P90 When the SSUS bit in PFCR is 1, the SCS pin is switched to the SSI pin.
Figure B.4 (d) Port 9 Block Diagram (P90)
Rev. 3.00 May 15, 2007 Page 483 of 516 REJ09B0152-0300
Appendix
Comparator
COMPm
PBn
Internal data bus
A/D module DEC AMR3 to AMR0 Vin m = 1 or 0
n = 5 or 4
Figure B.5 (a) Port B Block Diagram (PB5 or PB4)
PBn
Internal data bus
A/D module DEC AMR3 to AMR0 Vin
n = 3 or 2
Figure B.5 (b) Port B Block Diagram (PB3 or PB2)
Rev. 3.00 May 15, 2007 Page 484 of 516 REJ09B0152-0300
Appendix
IRQn
PMRBn
PFCR (IRQnS1, IRQnS0)
PBn
Internal data bus
A/D module AMR3 to AMR0 Vin
DEC
PMRB: Port mode register B PFCR: Pin function control register n = 1 or 0
Figure B.5 (c) Port B Block Diagram (PB1 or PB0)
Rev. 3.00 May 15, 2007 Page 485 of 516 REJ09B0152-0300
Appendix
B.2
Port States in Each Operating State
Sleep (High-Speed/ MediumSpeed) Subsleep Retained Retained Retained Retained Active (High-Speed/ MediumWatch Subactive Speed) Functions Functions Functions Functions Retained Retained Retained Retained High impedance
Port
Reset
Standby
P12 to P10 High Retained impedance P32 to P30 High Retained impedance P84 to P82 High Retained impedance P93 to P90 High Retained impedance PB5 to PB0 High High impedance impedance
High Functions 12 impedance* * High Functions 12 impedance* * High Functions 12 impedance* * High Functions 12 impedance* *
High High 1 impedance impedance*
High High impedance impedance
Notes: 1. Registers are retained and output level is high impedance. 2. High-level output when the pull-up MOS is turned on.
Rev. 3.00 May 15, 2007 Page 486 of 516 REJ09B0152-0300
Appendix
B.3
Port 9 Related Register Settings and Pin Functions Port 9 Related Register Settings and Pin Functions
SSU Setting IIC2 Setting RE 1 (Receive) ICE 0 (IIC2 not used) SSUS 0 PFCR Setting IRQ1S1, IRQ1S0 IRQ0S1, IRQ0S0 P93 P92 P91 SSCK input SSI input IRQ0N input P93 I/O SSCK input IRQ1N input P93 I/O SSCK input SSO output IRQ1N input P93 I/O SSO output SSCK input IRQ1N input SSCK input SSCK input SSCK input SSO output SSO output SSCK input SSO output SSO output SSI input SSI input P90 I/O P90 I/O P90 I/O P90 I/O P90 I/O P91 I/O SSI input SSCK input P91 I/O SSI input P90 I/O P90 P90 I/O Pin Functions
Table B.1
SSUMS 0 (Clock synchronous)
BIDE *
MSS 0 (Slave)
TE 0
Other then Other 01 then 01
SSI input P92 I/O
Other then 01 01 1 Other then Other 01 01 then 01 Other then 01
1 (Transmit)
0
0 (IIC2 not used)
0
Other then Other 01 01 then 01 Other then 01
1
Other then Other 01 01 then 01 Other then 01
1 (Transmit)
1 (Receive)
0 (IIC2 not used)
0
Other then Other 01 then 01
SSI input SSO output P93 I/O SSCK input IRQ1N input SSCK input
1
Other then Other 01 01 then 01 Other then 01
Rev. 3.00 May 15, 2007 Page 487 of 516 REJ09B0152-0300
Appendix
SSU Setting IIC2 Setting SSUMS 0 (Clock synchronous) 1 BIDE * MSS 1 (Master) TE 0 RE 1 (Receive) ICE 0 (IIC2 not used) SSUS 0
PFCR Setting IRQ1S1, IRQ1S0 IRQ0S1, IRQ0S0 P93
Pin Functions
P92
P91 SSCK output
P90 P90 I/O
Other then Other 01 then 01
SSI input P92 I/O
Other then 01 01 Other then Other 01 01 then 01 Other then 01
SSI input IRQ0N input P93 I/O SSCK output IRQ1N input P93 I/O SSCK output SSO output IRQ1N input P93 I/O SSO output SSCK output IRQ1N input SSCK output
SSCK output P91 I/O
P90 I/O
SSI input
P91 I/O
SSI input
1 (Transmit)
0
0 (IIC2 not used)
0
Other then Other 01 01 then 01 Other then 01
SSCK output SSCK output SSO output SSO output SSCK output SSO output SSO output
P90 I/O
P90 I/O
1
Other then Other 01 01 then 01 Other then 01
P90 I/O
P90 I/O
1 (Transmit)
1 (Receive)
0 (IIC2 not used)
0
Other then Other 01 then 01
SSI input SSO output P93 I/O SSCK output IRQ1N input SSCK output
P90 I/O
1
Other then Other 01 01 then 01 Other then 01
SSI input
SSI input
Rev. 3.00 May 15, 2007 Page 488 of 516 REJ09B0152-0300
Appendix
SSU Setting
IIC2 Setting TE 0 RE 1 (Receive) ICE 0 (IIC2 not used) SSUS 0
PFCR Setting IRQ1S1, IRQ1S0 Other then 01 01 IRQ0S1, IRQ0S0 Other then 01 Other then 01 1 Other then 01 Other then 01 Other then 01 01 IRQ1N input SCS input SSI output SSI output Other then 01 Other then 01 Other then 01 Other then 01 01 SCS input SSI output SCS input SSI input SSI input Other then 01 Other then 01 Other then 01 1 Other then 01 Other then 01 Other then 01 Other then 01 IRQ1N input SCS output SSI input SCS output SCS output P93
Pin Functions
SSUMS 1 (Four-line nication)
BIDE 0
MSS 0 (Slave)
P92
P91 SSCK input SSCK input SSO input
P90 SCS input SCS input P90 I/O
P93 I/O SSO input SSO input SSCK input
bus commu- (One-way)
1 (Transmit)
0
0 (IIC2 not used)
0
Other then 01 Other then 01
P92 I/O SSCK input IRQ0N input SSCK input SSO input SSCK input SSCK input SSO input SSCK input
SCS input SCS input
1
Other then 01
P91 I/O SSI output SCS input SSI output SCS output SCS output
1 (Transmit)
1 (Receive)
0 (IIC2 not used)
0
Other then 01
1
Other then 01
1 (Master)
0
1 (Receive)
0 (IIC2 not used)
0
Other then 01 Other then 01
P92 I/O SSCK output IRQ0N input SSCK output SSCK output SSCK output SSO output SSCK output SSO output SSCK output
1
Other then 01
P91 I/O SSI input SCS output SCS output P90 I/O
1 (Transmit)
0
0 (IIC2 not used)
0
Other then 01 01
P93 I/O SSO output SSO output SSCK output SSO output SSCK output
1 (Transmit)
1 (Receive)
0 (IIC2 not used)
0
Other then 01
SCS output SSI input
1
Other then 01
Rev. 3.00 May 15, 2007 Page 489 of 516 REJ09B0152-0300
Appendix
SSU Setting
IIC2 Setting ICE 0 (IIC2 not used)
PFCR Setting IRQ1S1, SSUS 0 IRQ1S0 Other then 01 01 IRQ0S1, IRQ0S0 Other then 01 Other then 01 1 Other then 01 Other then 01 Other then 01 Other then 01 1 Other then 01 Other then 01 Other then 01 Other then 01 1 Other then 01 Other then 01 Other then 01 Other then 01 1 Other then 01 Other then 01 Other then 01 01 IRQ1N input SCS output IRQ1N input SCS output IRQ1N input SCS input IRQ1N input SCS input P93
Pin Functions
SSUMS 1 (Four-line nication)
BIDE 1 tional)
MSS 0 (Slave)
TE 0
RE 1 (Receive)
P92
P91 SSCK input SSCK input SSO input SSCK input SSCK input SSO output SSCK output SSCK output SSO input SSCK output SSCK output SSO output
P90 SCS input SCS input P90 I/O
P93 I/O SSO input SSO input SSCK input
bus commu- (Bidirec-
1 (Transmit)
0
0 (IIC2 not used)
0
Other then 01 01
P93 I/O SSO output SSO output SSCK input
SCS input SCS input P90 I/O
1 (Master)
0
1 (Receive)
0 (IIC2 not used)
0
Other then 01 01
P93 I/O SSO input SSO input SSCK output
SCS output SCS output P90 I/O
1 (Transmit)
0
0 (IIC2 not used)
0
Other then 01 01
P93 I/O SSO output SSO output SSCK output
SCS output SCS output P90 I/O
0 (SSU not used)
0
0
0
0
1 (IIC2 used)
*
Other then 01 Other then 01 01
P93 I/O P92 I/O SDA I/O SCL I/O
P93 I/O IRQ0N input
SDA I/O SCL I/O
Other then 01
IRQ1N input IRQ1N input
P92 I/O SDA I/O SCL I/O
01
01
IRQ0N input
SDA I/O SCL I/O
0 (IIC2 not used)
*
Other then 01 Other then 01 01
Other then 01 01
P93 I/O P92 I/O P91 I/O P90 I/O
P93 I/O IRQ0N input
P91 I/O P90 I/O
Other then 01
IRQ1N input IRQ1N input
P92 I/O P91 I/O P90 I/O
01
01
IRQ0N input
P91 I/O P90 I/O
[Legend]
*: Don't care.
Rev. 3.00 May 15, 2007 Page 490 of 516 REJ09B0152-0300
Appendix
C.
Product Part No. Lineup
Package (Package Model Marking Code) 38602R10 38602R4 F38602RFH10 F38602RFH4 38602R(***) 38602R(***) 38600R(***) 38600R(***) 32-pin QFN (TNP-32) 32-pin LQFP (32P6U-A) 32-pin QFN (TNP-32) 32-pin LQFP (32P6U-A) 32-pin QFN (TNP-32) 32-pin LQFP (32P6U-A)
Product Classification H8/38602R Group H8/38602R Flash memory (10 MHz) version (4 MHz) (10 MHz) (4 MHz) Masked ROM version
Product Part No. HD64F38602RFT10 HD64F38602RFT4 HD64F38602RFH10 HD64F38602RFH4 HD64338602RFT HD64338602RFH
H8/38600R
Masked ROM version
HD64338600RFT HD64338600RFH
[Legend] (***): ROM code
Rev. 3.00 May 15, 2007 Page 491 of 516 REJ09B0152-0300
D.
JEITA Package Code PVQN0032KA-A TNP-32/TNP-32V 0.06g
RENESAS Code
Previous Code
MASS[Typ.]
Appendix
26
16
HE E
32 ZE
10 Lp
e
c c1
A
A1
The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority.
Figure D.1 Package Dimensions (TNP-32)
A2
REJ09B0152-0300
HD D 17
P-VQFN32-5x6-0.50
Package Dimensions
Rev. 3.00 May 15, 2007 Page 492 of 516
Reference Dimension in Millimeters Symbol Min Nom Max D E A2 A A1 b b1 e Lp x y y1 t HD HE ZD ZE c c1 0.17 6.2 5.2 1.0 1.0 0.22 0.20 0.25 0.50 0.005 0.17 0.02 0.22 0.20 0.5 0.60 0.70 0.05 0.05 0.20 0.20 6.0 5.0 0.89 0.95 0.04 0.27
25
1 t y1 b b1 xM
x4
9Z D
y
Note: Don't connect the exposed part of die-pad-support-leads to the pads on a printed wiring board (PWB).
JEITA Package Code P-LQFP32-7x7-0.80
RENESAS Code PLQP0032GB-A
Previous Code 32P6U-A
MASS[Typ.] 0.2g
HD *1 D
24
17
25
16
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
E
HE
*2
c1
c
Reference Dimension in Millimeters Symbol
Terminal cross section 32
1 ZD Index mark F
8
ZE
9
A
A2
c
A1
Figure D.2 Package Dimensions (32P6U-A)
L L1 y e *3 Detail F bp x
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0
Appendix
Rev. 3.00 May 15, 2007 Page 493 of 516
REJ09B0152-0300
Appendix
Rev. 3.00 May 15, 2007 Page 494 of 516 REJ09B0152-0300
Main Revisions and Additions in this Edition
Item Section 1 Overview 1.1 Features * Compact package 36 Modified EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4 or R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4, R4L, and R6 so that the end address of the destination address (value of R6 + R4L or R6 + R4) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). 44 Modified A reset has the highest exception priority. There are three sources to generate a reset. Table 3.2 lists the reset sources. Table 3.2 Reset Sources 3.2.1 Reset Exception Handling 3.8.1 Notes on Stack Area Use 44 44 58 Added The description in this section is modified. Modified ......, so the stack pointer (SP: R7) should never indicate an odd address. To save register values, use PUSH.W Rn (MOV.W Rn, @-SP) or PUSH.L ERn (MOV.L ERn, @-SP). To restore register values, use POP.W Rn (MOV.W @SP+, Rn) or POP.L ERn (MOV.L @SP+, ERn). Section 2 CPU 2.8.2 EEPMOV Instruction Page Revisions (See Manual for Details) 1 The description on the package, P-LQFP-32, is added.
Section 3 Exception Handling 3.2 Reset
Rev. 3.00 May 15, 2007 Page 495 of 516 REJ09B0152-0300
Item
Page Revisions (See Manual for Details) Modified ...... The input level on the E7_2 pin during a reset is pulled up or down using a resistor according to the selected oscillator, and fixed on exit from the reset state. When the on-chip oscillator is selected, a resonator no longer needs to be connected to the OSC1 and OSC2 pins. In such a case, fix the OSC1 pin to GND or leave it open, and leave the OSC2 pin open. Note is added. Notes: 1. ...... 2. When the on-chip debugger is connected, the value of the resistor should be high. When not connected, it is specified according to the selected oscillator.
Section 4 Clock Pulse Generators 67 4.2.4 On-Chip Oscillator Selection Method
Figure 4.5 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator
68
Modified
Frequency 38.4 kHz Manufacturer EPSON TOYOCOM CORPORATION Products Name Equivalent Series Resistance C-4-TYPE C-001R 30 k (max.) 35 k (max.)
32.768 kHz EPSON TOYOCOM CORPORATION C 1 = C 2 = 7 pF (typ.)
Note: Consult with the crystal resonator manufacturer to determine the parameters.
4.3.1 Connecting 32.768kHz/38.4-kHz Crystal Resonator
68
Added 1. When the resonator other than ones listed above is used, perform matching evaluation with the crystal resonator manufacture and connect it under the optimum condition. Even when the resonator listed above or the equivalent is used, as the oscillation characteristics depend on the board specification, perform matching evaluation on the mounting board. 2. Perform matching evaluation in the reset state (the RES pin is low) and on exit from the reset state (the RES pin is driven from low to high).
4.4.1 Prescaler S
71
Deleted The output from prescaler S is shared by the on-chip peripheral modules. The division ratio can be set separately for each on-chip peripheral function.
Rev. 3.00 May 15, 2007 Page 496 of 516 REJ09B0152-0300
Item 4.5.1 Note on Resonators and Resonator Circuits
Page Revisions (See Manual for Details) 72 Modified Resonator characteristics are closely related to board design. Therefore, resonators should be assigned after being carefully evaluated by the user in the masked ROM version and flash memory version, with referring to the examples shown in this section. 74 75 The description in this section is modified. Modified
Oscillation waveform (OSC2)
4.5.3 Definition of Oscillation Stabilization Wait Time Figure 4.12 Oscillation Stabilization Wait Time
System clock () Oscillation start time
Wait time
Operating mode
Standby mode, watch mode, or subactive mode
Oscillation stabilization wait time
Active (high-speed) mode or active (medium-speed) mode
Interrupt accepted
4.5.5 Note on the Oscillation Stabilization of Resonators 4.5.6 Note on Using Power-On Reset
76 76
The title modified Modified The power-on reset circuit in this LSI adjusts the reset clear time by the capacitor capacitance, which is externally connected to the RES pin. The external capacitor capacitance should be adjusted to secure the oscillation stabilization time before reset clearing. For details, refer to section 19, Power-On Reset Circuit.
Section 5 Power-Down Modes 5.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) * CKSTPR2
81
The note is modified. Notes: 3. ... When the watchdog timer stops operating and the WDON bit is cleared to 0 by software, this bit is valid and the watchdog timer enters module standby mode.
Table 5.3 Internal State in Each Operating Mode
86
The note is modified. Notes: 6. Functions if the 32.768-kHz RTC is selected as an internal clock. Halted and retained otherwise.
Rev. 3.00 May 15, 2007 Page 497 of 516 REJ09B0152-0300
Item 5.2.2 Standby Mode
Page Revisions (See Manual for Details) 88 Modified ... However, as long as the rated voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. ... Modified ... or the requested interrupt is disabled by the interrupt enable bit. When a reset source is generated in standby mode, the system clock oscillator starts. If a reset is generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high.
5.2.3 Watch Mode
88
Modified ... or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in watch mode, the system clock oscillator starts. If a reset is generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes. The CPU starts reset exception handling when the RES pin is driven high.
5.2.4 Subsleep Mode
89
Modified ... or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in subsleep mode, the system clock oscillator starts. If a reset is generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes. The CPU starts reset exception handling when the RES pin is driven high.
5.2.5 Subactive Mode
89
Modified ... on the combination of bits SSBY, LSON, and TMA3 in SYSCR1 and bits MSON and DTON in SYSCR2. Subactive mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by the interrupt enable register. When a reset source is generated in subactive mode, the system clock oscillator starts. If a reset is generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes and the tREL period has elapsed. The CPU starts reset exception handling when the RES pin is driven high.
Rev. 3.00 May 15, 2007 Page 498 of 516 REJ09B0152-0300
Item 5.2.6 Active (Medium-Speed) Mode
Page Revisions (See Manual for Details) 90 Modified In active (medium-speed) mode, the clock set by the MA1 and MA0 bits in SYSCR1 is used as the system clock, and the CPU and on-chip peripheral modules function. Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed) mode is cleared, a transition to standby mode is made depending on the combination of bits SSBY, LSON, and TMA3 in SYSCR1, a transition to watch mode is made depending on the combination of bits SSBY and TMA3 in SYSCR1, or a transition to sleep mode is made depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition to active (high-speed) mode or subactive mode is made by a direct transition. Active (medium-sleep) mode is not entered if the I bit in CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. When the RES pin goes low, the CPU goes into the reset state and active (medium-sleep) mode is cleared. In active (medium-speed) mode, the on-chip peripheral modules function at the clock set by the MA1 and MA0 bits in SYSCR1.
5.3 Direct Transition
91
The description in this section is modified. Added When a SLEEP instruction is executed in active (highspeed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made to active (medium-speed) mode via sleep mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). Example: When osc/8 is selected as the CPU operating clock after the transition Direct transition time = (2 + 1) x 1tosc + 14 x 8tosc = 115tosc For the legend of symbols used above, refer to section 21, Electrical Characteristics.
5.3.1 Direct Transition from Active 91 (High-Speed) Mode to Active (Medium-Speed) Mode
Rev. 3.00 May 15, 2007 Page 499 of 516 REJ09B0152-0300
Item
Page Revisions (See Manual for Details) Added When a SLEEP instruction is executed in active (highspeed) mode while the SSBY, TMA3, and LSON bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Example: When w/8 is selected as the subactive operating clock after the transition Direct transition time = (2 + 1) x 1tosc + 14 x 8tw = 3tosc + 112tw For the legend of symbols used above, refer to section 21, Electrical Characteristics.
5.3.2 Direct Transition from Active 92 (High-Speed) Mode to Subactive Mode
5.3.3 Direct Transition from Active 92 (Medium-Speed) Mode to Active (High-Speed) Mode
Added When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (3). Example: When osc/8 is selected as the CPU operating clock before the transition Direct transition time = (2 + 1) x 8tosc + 14 x 1tosc = 38tosc For the legend of symbols used above, refer to section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 500 of 516 REJ09B0152-0300
Item
Page Revisions (See Manual for Details) Added When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY, LSON, and TMA3 bits in SYSCR1 are set to 1 and the DTON bit in SYSCR2 is set to 1, a transition is made to subactive mode via watch mode. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (4). Example: When osc/8 and w/8 are selected as the CPU operating clock before and after the transition, respectively Direct transition time = (2 + 1) x 8tosc + 14 x 8tw = 24tosc + 112tw For the legend of symbols used above, refer to section 21, Electrical Characteristics.
5.3.4 Direct Transition from Active 93 (Medium-Speed) Mode to Subactive Mode
5.3.5 Direct Transition from Subactive Mode to Active (HighSpeed) Mode
93
Added and modified When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (5). Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal processing states)} x (tsubcyc before transition) + (Wait time set in bits STS2 to STS0) + (Number of interrupt exception handling execution states) x (tcyc after transition).....(5) Example: When w/8 is selected as the CPU operating clock after the transition and wait time = 8192 states Direct transition time = (2 + 1) x 8tw + (8192 + 14) x1tosc = 24tw + 8206tosc For the legend of symbols used above, refer to section 21, Electrical Characteristics.
Rev. 3.00 May 15, 2007 Page 501 of 516 REJ09B0152-0300
Item 5.3.6 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
Page Revisions (See Manual for Details) 94 Added When a SLEEP instruction is executed in subactive mode while the SSBY and TMA3 bits in SYSCR1 are set to 1, the LSON bit in SYSCR1 is cleared to 0, and the MSON and DTON bits in SYSCR2 are set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2 to STS0 in SYSCR1 has elapsed. The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (6). Example: When w/8 and osc/8 are selected as the CPU operating clock before and after the transition, respectively, and wait time = 8192 states Direct transition time = (2 + 1) x 8tw + 8192 x 1tosc + 14 x 8tosc = 24tw + 8304tosc For the legend of symbols used above, refer to section 21, Electrical Characteristics.
Section 6 ROM 6.7 Notes on Setting Module Standby Mode
117
Modified ... Then the flash memory should be set to enter the module standby mode. If an interrupt is generated in module standby mode, the vector address cannot be fetched. As a result, the program may run away.
Section 8 I/O Ports 8.1.5 Pin Functions * P10/AEVH/FTIOA/TMOW/CL KOUT pin
122
Added Note: * Switching the clock (OSC, OSC/2, or OSC/4) for CLKOUT output must be performed when CLKOUT output is halted (CLKOUT = 0). When making a transition to a power-down mode wherein the system clock oscillator is halted, the output level is retained. (In standby mode, output is the high-impedance state.) When making a transition from a power-down mode wherein the system clock oscillator is halted, to the active mode wherein the system clock oscillator operates, halt CLKOUT output (CLKOUT = 0) before the transition.
8.7.2 Input Characteristics Difference due to Pin Function
124
This section is newly added.
Rev. 3.00 May 15, 2007 Page 502 of 516 REJ09B0152-0300
Item Section 9 Timer B1 Figure 9.2 Timer B1 Initial Setting Flow
Page Revisions (See Manual for Details) 148 Modified
Cancel the module standby mode of timer B1 *1 Set counter function with bit TMB17 in TMB1 and counter clock with bits TMB12 to TMB10 in TMB1 (bit TMB16 must be cleared to 0 when writing to these bits)
Section 11 Realtime Clock (RTC) 193 11.3.7 Clock Source Select Register (RTCCSR)
Modified
Bit Bit Name Description 3 2 1 0 RCS3 RCS2 RCS1 RCS0 Clock Source Selection 0000: /8 Free running counter operation 0001: /32 Free running counter operation 0010: /128 Free running counter operation 0011: /256 Free running counter operation 0100: /512 Free running counter operation 0101: /2048 Free running counter operation 0110: /4096 Free running counter operation 0111: /8192 Free running counter operation 1000: W/4 RTC operation 1001 to 1111: Setting prohibited
11.4.1 Initial Settings of Registers 196 after Power-On
Modified The RTC registers that store second, minute, hour, and day-of-week data, control registers, and interrupt registers are not reset by a RES input, or by a reset source caused by a watchdog timer. Modified ... When using an interrupt, set the IENRTC (RTC interrupt request enable) bit in IENR1 to 1 last after other registers are set.
11.5 Interrupt Sources
198
11.6.2 Note when Using RTC Interrupts
199
Added
Rev. 3.00 May 15, 2007 Page 503 of 516 REJ09B0152-0300
Item Section 12 Watchdog Timer 12.2.1 Timer Control/Status Register WD1 (TCSRWD1)
Page Revisions (See Manual for Details) 203 Added
Bit Bit Name Description 0 WRST Watchdog Timer Reset Indicates whether a reset caused by the watchdog timer is generated. This bit is not cleared by a reset caused by the watchdog timer. [Setting condition] When TCWD overflows and an internal reset signal is generated
12.3.1 Watchdog Timer Mode
208
Modified ... When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 512 clock cycles by the on-chip oscillator (ROSC).
Figure 12.2 Example of Watchdog 208 Timer Operation
Modified
H'FF H'F1 TCWD count value TCWD overflow
H'00 Start H'F1 written to TCWD Internal reset signal 512 clock cycles by Rosc H'F1 written to TCWD Reset generated
Figure 12.3 Interval Timer Mode Operation
209
Modified
H'FF
TCWD count value Time H'00 WT/IT = 1 Interval timer Interval timer Interval timer Interval timer Interval timer interrupt interrupt interrupt interrupt interrupt request generated request generated request generated request generated request generated
12.5.3 Clearing the WT/IT or IEOVF Bit in TCSRWD2 to 0
210
Added Added
Table 12.1 Assembly Program for 211 Clearing WT/IT or IEOVF Bit to 0
Rev. 3.00 May 15, 2007 Page 504 of 516 REJ09B0152-0300
Item Table 12.2 The Value of "xx" Section 13 Asynchronous Event Counter (AEC) 13.3.6 Event Counter H (ECH)
Page Revisions (See Manual for Details) 211 222 Added Modified
Bit 7 6 5 4 3 2 1 0 Bit Name Description ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Either the external asynchronous event AEVH pin, /2, /4, or /8, or the overflow signal from lower 8bit counter ECL can be selected as the input clock source. ECH can be cleared to H'00 when the CRCH bit in ECCSR is cleared to 0.
13.3.7 Event Counter L (ECL)
222
Modified
Bit 7 6 5 4 3 2 1 0 Bit Name Description ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0 Either the external asynchronous event AEVL pin, /2, /4, or /8 can be selected as the input clock source. ECL can be cleared to H'00 when the CRCL bit in ECCSR is cleared to 0.
Section 14 Serial Communication 231 Interface 3 (SCI3, IrDA)
Deleted The serial communication interface 3 (SCI3) can handle both asynchronous and clock synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). Modified
Bit 2 Bit Name Description MP 5-Bit CommunicationWhen this bit is set to 1, the 5-bit communication format is enabled. Make sure to set bit 5 (PF) to 1 when setting this bit (MP) to 1.
14.3.5 Serial Mode Register (SMR)
235
Rev. 3.00 May 15, 2007 Page 505 of 516 REJ09B0152-0300
Item 14.3.6 Serial Control Register (SCR) 14.3.7 Serial Status Register (SSR)
Page Revisions (See Manual for Details) 237 240 Bit 3 is reserved. Deleted SSR consists of status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. 240 Bits 1 and 0 are reserved. Modified
Bit 7 Bit Name Description IrE IrDA EnableSelects whether the SCI3 I/O pins function as the SCI3 or IrDA.0: TXD3/IrTXD and RXD3/IrRXD pins function as TXD3 and RXD31: TXD3/IrTXD and RXD3/IrRXD pins function as IrTXD and IrRXD
14.3.10 IrDA Control Register (IrCR)
252
14.3.11 Serial Extended Mode Register (SEMR)
253
Added
Bit 3 Bit Name Description ABCS Asynchronous Mode Basic Clock Select Selects the basic clock for the bit period in asynchronous mode. This setting is enabled only in asynchronous mode (COM bit in SMR3 is 0). 0: Operates on a basic clock with a frequency of 16 times the transfer rate 1: Operates on a basic clock with a frequency of eight times the transfer rate Clear the ABCS bit to 0, when the IrDA function is enabled.
Table 14.8 Data Transfer Formats 255 (Asynchronous Mode) Table 14.9 SMR Settings and Corresponding Data Transfer Formats 256
The formats are modified. The settings are modified.
Rev. 3.00 May 15, 2007 Page 506 of 516 REJ09B0152-0300
Item Figure 14.4 Sample SCI3 Initialization Flowchart
Page Revisions (See Manual for Details) 258 Modified
Wait No 1-bit interval elapsed? Yes Set SPC3 bit in SPCR to 1 Set TE and RE bits in SCR to 1, and set RIE, TIE and TEIE bits.
[4]
[[4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Setting bits TE and RE enables the TXD3 and RXD3 pins to be used. Also set the RIE, TIE, and TEIE bits, depending on whether interrupts are required. In asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit.

Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
260
Modified
[3]
No Break output? Yes [3] Clear PDR to 0 and set PCR to 1 To output a break in serial transmission, after setting PCR to 1 and PDR to 0, clear the SPC3 bit in SPCR and the TE bit in SCR to 0.
Clear SPC3 bit in SPCR and TE bit in SCR to 0*
Note: * When the SPC3 bit in SPCR is cleared to 0, the pin functions as an I/O port.
14.5 Operation in Clock Synchronous Mode
264
Deleted ... After 8-bit data is output, the transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit is added.
14.6 Multiprocessor Communication Function
270
This section is deleted.
Rev. 3.00 May 15, 2007 Page 507 of 516 REJ09B0152-0300
Item 14.8.2 Mark State and Break Sending
Page Revisions (See Manual for Details) 277 Modified When the SPC3 bit in SPCR is 0, the TXD3 pin functions as an I/O port whose direction (input or output) and level are determined by PCR and PDR, regardless of the TE setting. This can be used to set the TXD3 pin to the mark state (high level) or send a break during data transmission. To maintain the communication line at the mark state until the SPC3 bit in SPCR is set to 1, set both PCR and PDR to 1. As the SPC3 bit in SPCR is cleared to 0 at this point, the TXD3 pin functions as an I/O port, and 1 is output from the TXD3 pin. To send a break during data transmission, first set PCR to 1 and PDR to 0, and then clear the SPC3 and TE bits to 0. When the TE bit is cleared to 0 directly after the SPC3 bit is cleared to 0, the transmitter is initialized regardless of the current transmission state after the TE bit is cleared, the TXD3 pin functions as an I/O port after the SPC3 bit is cleared, and 0 is output from the TXD3 pin. 323 Modified
Section 16 I2C Bus Interface 2 (IIC2) 16.3.5 I2C Bus Status Register (ICSR)
Bit 3
Bit Name STOP
Description Stop Condition Detection Flag[Setting conditions] * In master mode, when a stop condition is detected after the completion of frame transfer * In slave mode, when a stop condition is detected, after the slave address of the first byte, following the general call and the detection of the start condition, matches the address set in SAR
Rev. 3.00 May 15, 2007 Page 508 of 516 REJ09B0152-0300
Item Figure 16.15 Receive Mode Operation Timing
Page Revisions (See Manual for Details) 339 Modified
SCL SDA (Input) MST TRS 7 8 1 2
Bit 6
Bit 7
Bit 0
Bit 1
RDRF ICDRS ICDRR Data 2 Data 1 Data 3 Data 2 [3]Read ICDRR
User processing
Section 17 A/D Converter 17.3.1 A/D Result Register (ADRR)
350
Modified ADRR is a 16-bit read-only register that stores the results of A/D conversion. The data is stored in the upper 10 bits of ADRR. ADRR can be read by the CPU at any time, ...
17.7.3 Usage Notes
360
Deleted 3. When A/D conversion is started after clearing module standby mode, wait for 10 clock cycles before starting A/D conversion. 4. When the LADS bit in ADSR is changed as from halting to operating, wait for 10 clock cycles before starting A/D conversion.
Rev. 3.00 May 15, 2007 Page 509 of 516 REJ09B0152-0300
Item Section 18 Comparators 18.5 Usage Notes
Page Revisions (See Manual for Details) 368 Modified 4. If the LSI enters the software standby mode or watch mode when a comparator is operating, the internal operation of the comparator is maintained. Since the comparator operates even in software standby mode or watch mode, it returns to the same mode after the specified interrupt is canceled, though the current for the comparator is consumed. If a comparator is not required to return to the software standby mode or watch mode when an interrupt is canceled and the current consumption needs to be reduced, stop the comparator by clearing the CME0 and CME1 bits in CMCR0 and CMCR1 to 0 before shifting the mode. 370 Modified The operation timing of the power-on reset circuit is shown in figure 19.2. As the power supply voltage rises, the capacitor, which is externally connected to the RES pin, is gradually charged through the on-chip pull-up resistor (Rp). 411 Modified
Item Symbol Applicable Test Condition Pins
Oscill ation stabili zation time Crystal resonator (VCC = 2.7 V to 3.6 V) Crystal resonator (VCC = 2.2 V to 3.6 V) -- 600 1000 -- 300 800 trc OSC1,OSC2 Ceramic resonator (VCC = 2.2 V to 3.6 V) Ceramic resonator (Other than above) -- 80 --
Section 19 Power-On Reset Circuit 19.2.1 Power-On Reset Circuit
Section 21 Electrical Characteristics Table 21.3 Control Signal Timing
Values Min. Typ. Max.
-- 20 45
Rev. 3.00 May 15, 2007 Page 510 of 516 REJ09B0152-0300
Item
Page Revisions (See Manual for Details) Modified
Item Symbol Applicable Test Condition Pins
Oscill ation stabili zation time trc
Table 21.14 Control Signal Timing 425
Values Min. Typ. Max.
20 45
OSC1,OSC2 Ceramic resonator(VCC -- = 2.2 V to 3.6 V) Ceramic resonator(Other than above) Crystal resonator(VCC = -- 2.7 V to 3.6 V) Crystal resonator(VCC = -- 2.2 V to 3.6 V) --
80
--
300
800
600
1000
Appendix A.1 Instruction List 2. Arithmetic Instructions
447
Modified
Addressing Mode and Instruction Length (bytes) No. of States*1
@-ERn/@ERn+
Mnemonic
Operand Size
Condition Code Operation
@(d, ERn)
I Rd8 decimal adjust Rd8 --
H *
N
Z
V *
C
DAA
B
2
2
2
C. Product Part No. Lineup D. Package Dimensions Figure D.2 Package Dimensions (32P6U-A)
491 492
The list is modified. Added
Rev. 3.00 May 15, 2007 Page 511 of 516 REJ09B0152-0300
Advanced
@(d, PC)
Normal
@@aa
@ERn
@aa
#xx
Rn
--
Rev. 3.00 May 15, 2007 Page 512 of 516 REJ09B0152-0300
Index
A
A/D converter ......................................... 349 Addressing modes..................................... 27 Absolute address................................... 28 Immediate ............................................. 29 Memory indirect ................................... 29 Program-counter relative ...................... 29 Register direct....................................... 28 Register indirect.................................... 28 Register indirect with displacement...... 28 Register indirect with post-increment... 28 Register indirect with pre-decrement.... 28 Asynchronous event counter (AEC) ....... 213 16-bit counter operation...................... 223 8-bit counter operation........................ 224 Event counter PWM operation ........... 225 Boot program ...................................... 104 Erasing a block.................................... 100 Erasing/erasing-verifying.................... 112 Error protection................................... 114 Hardware protection............................ 114 On-board programming modes ........... 104 Power-down states .............................. 115 Programming units.............................. 100 Programming/erasure in user program mode.................................................... 108 Programming/programming-verifying 109 Software protection............................. 114
G
General registers ....................................... 10
C
Clock pulse generators.............................. 63 System clock oscillator ......................... 66 Comparators............................................ 361 Hysteresis characteristics.................... 366 Condition field.......................................... 26 Condition-code register (CCR)................. 11 CPU ............................................................ 7
I
I/O ports .................................................. 119 I2C bus format ......................................... 328 I2C bus interface 2 (IIC2)........................ 311 Acknowledge ...................................... 328 Bit synchronous circuit ....................... 346 Clocked synchronous serial format..... 337 Noise canceler..................................... 340 Slave address....................................... 328 Start condition..................................... 328 Stop condition ..................................... 328 Transfer rate ........................................ 316 Instruction set............................................ 16 Arithmetic operations instructions ........ 18 Bit manipulation instructions ................ 21 Block data transfer instructions............. 25 Branch instructions ............................... 23 Data transfer instructions ...................... 17 Logic operations instructions ................ 20
Rev. 3.00 May 15, 2007 Page 513 of 516 REJ09B0152-0300
E
Effective address....................................... 30 Effective address extension ...................... 26 Exception handling ................................... 41
F
Flash memory ........................................... 99 Boot mode........................................... 105
Shift instructions................................... 20 System control instructions................... 24 Interrupt mask bit (I)................................. 11 IrDA........................................................ 271
L
Large current port ................................... 119 Large current ports...................................... 1
M
Memory map .............................................. 8
O
Operation field.......................................... 26
P
Package....................................................... 2 Pin assignment............................................ 3 Power-down modes .................................. 77 Power-Down Modes Module standby function ...................... 96 Sleep mode ........................................... 87 Standby mode ....................................... 88 Subactive mode .................................... 89 Subsleep mode...................................... 89 Power-on reset circuit............................. 369 Program counter (PC)............................... 11
R
Realtime clock (RTC)............................. 185 Data reading procedure....................... 197 Initial setting procedure ...................... 196 Register field ............................................ 26 Registers
Rev. 3.00 May 15, 2007 Page 514 of 516 REJ09B0152-0300
ADRR ......................... 350, 374, 378, 382 ADSR.......................... 352, 374, 378, 382 AEGSR ....................... 218, 374, 378, 381 AMR ........................... 351, 374, 378, 382 BRR ............................ 243, 374, 378, 382 CKSTPR1 ..................... 81, 375, 379, 383 CKSTPR2 ..................... 81, 375, 379, 383 CMCR......................... 362, 373, 377, 381 CMDR......................... 364, 373, 377, 381 EBR1........................... 103, 372, 376, 380 ECCR.......................... 219, 374, 378, 381 ECCSR........................ 220, 374, 378, 381 ECH ............................ 222, 374, 378, 381 ECL............................. 222, 374, 378, 381 ECPWCR.................... 216, 374, 377, 381 ECPWDR.................... 217, 374, 377, 381 FENR .......................... 104, 372, 376, 380 FLMCR1..................... 101, 372, 376, 380 FLMCR2..................... 102, 372, 376, 380 FLPWCR .................... 103, 372, 376, 380 GRA............................ 165, 373, 377, 381 GRB ............................ 165, 373, 377, 381 GRC ............................ 165, 373, 377, 381 GRD............................ 165, 373, 377, 381 ICCR1 ......................... 314, 372, 376, 380 ICCR2 ......................... 317, 372, 376, 380 ICDRR ........................ 327, 372, 376, 380 ICDRS................................................. 327 ICDRT ........................ 326, 372, 376, 380 ICIER.......................... 321, 372, 376, 380 ICMR .......................... 319, 372, 376, 380 ICSR ........................... 323, 372, 376, 380 IEGR ............................. 47, 375, 379, 383 IENR ............................. 48, 375, 379, 383 IrCR ............................ 252, 374, 378, 382 IRR................................ 50, 375, 379, 383 OSCCR ......................... 64, 375, 379, 383 PCR1........................... 120, 375, 379, 382 PCR3........................... 125, 375, 379, 382 PCR8........................... 129, 375, 379, 382
PCR9........................... 133, 375, 379, 382 PDR1 .......................... 120, 375, 378, 382 PDR3 .......................... 125, 375, 378, 382 PDR8 .......................... 129, 375, 378, 382 PDR9 .......................... 133, 375, 378, 382 PDRB.......................... 138, 375, 378, 382 PFCR .......................... 143, 373, 376, 380 PMR1.......................... 121, 375, 378, 382 PMR3.......................... 126, 375, 378, 382 PMRB ......................... 139, 375, 378, 382 PODR9 ....................... 134, 373, 376, 380 PUCR1........................ 121, 375, 378, 382 PUCR3........................ 126, 375, 379, 382 PUCR8........................ 130, 373, 376, 380 PUCR9........................ 134, 373, 376, 380 RDR............................ 234, 374, 378, 382 RHRDR ...................... 189, 372, 376, 380 RMINDR .................... 188, 372, 376, 380 RSECDR..................... 187, 372, 376, 380 RSR..................................................... 234 RTCCR1 ..................... 191, 372, 376, 380 RTCCR2 ..................... 192, 372, 376, 380 RTCCSR..................... 193, 372, 376, 380 RTCFLG..................... 194, 372, 376, 380 RWKDR ..................... 190, 372, 376, 380 SAR ............................ 326, 372, 376, 380 SCR............................. 237, 374, 378, 382 SEMR ......................... 253, 374, 378, 382 SMR............................ 235, 374, 378, 382 SPCR ...................142, 251, 374, 378, 381 SSCRH ....................... 285, 373, 377, 381 SSCRL........................ 287, 373, 377, 381 SSER........................... 290, 373, 377, 381 SSMR ......................... 289, 373, 377, 381 SSR ............................. 240, 374, 378, 382 SSRDR ....................... 293, 373, 377, 381 SSSR........................... 291, 373, 377, 381 SSTDR........................ 293, 373, 377, 381 SSTRSR.............................................. 293 SYSCR1 ....................... 78, 375, 379, 383
SYSCR2........................ 80, 375, 379, 383 TCB1........................... 147, 373, 376, 380 TCNT .......................... 164, 373, 377, 381 TCRW......................... 158, 373, 377, 381 TCSRWD1.................. 203, 374, 378, 382 TCSRWD2.................. 205, 374, 378, 382 TCWD......................... 206, 374, 378, 382 TDR ............................ 234, 374, 378, 382 TIERW........................ 159, 373, 377, 381 TIOR0 ......................... 161, 373, 377, 381 TIOR1 ......................... 163, 373, 377, 381 TLB1................................................... 147 TMB1.......................... 146, 373, 376, 380 TMRW ........................ 157, 373, 377, 381 TMWD........................ 207, 374, 378, 382 TSR ..................................................... 234 TSRW ......................... 160, 373, 377, 381
S
Serial communication interface 3 (SCI3) Asynchronous mode............................ 253 Bit rate................................................. 243 Break................................................... 277 Clocked synchronous mode ................ 265 Framing error ...................................... 261 Mark state ........................................... 277 Overrun error ...................................... 261 Parity error .......................................... 261 Stack pointer (SP) ..................................... 11 Synchronous serial communication unit (SSU) ...................................................... 283 Clock polarity...................................... 294 Clocked synchronous communication mode.................................................... 297 Communication mode ......................... 296 Transfer clock ..................................... 293
Rev. 3.00 May 15, 2007 Page 515 of 516 REJ09B0152-0300
T
Timer B1................................................. 145 Auto-reload timer operation ............... 150 Interval timer operation ...................... 150 Timer W ................................................. 153 PWM operation .................................. 170
V
Vector address........................................... 42
W
Watchdog timer....................................... 201
Rev. 3.00 May 15, 2007 Page 516 of 516 REJ09B0152-0300
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/38602R Group
Publication Date: Rev.1.00, May 20, 2004 Rev.3.00, May 15, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8/38602R Group Hardware Manual

▲Up To Search▲

Price & Availability of H838602R

	To Download H838602R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .